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| start [2025/03/25 10:35] – geraldod | start [2025/04/24 21:32] (current) – [Memory-Centric Computing Systems (MCCSys) - March 30th] omutlu | ||
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| ===== 1st Workshop on ===== | ===== 1st Workshop on ===== | ||
| - | ===== Memory-Centric Computing Systems (MCCSys) - March 30th ===== | + | ===== Memory-Centric Computing Systems (MCCSys) - 30 March 2025 ===== |
| ==== Workshop Description ==== | ==== Workshop Description ==== | ||
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| This combined tutorial and workshop will focus on the latest advances in PIM technology, spanning both hardware and software. It will include novel PIM ideas, different tools and frameworks for conducting PIM research, and programming techniques and optimization strategies for PIM kernels. First, we will provide a series of lectures and invited talks that will provide an introduction to PIM, including an overview and a rigorous analysis of existing PIM hardware from industry and academia. Second, we will invite the broad PIM research community to submit and present their ongoing work on memory-centric systems. The program committee will favor papers that bring new insights on memory-centric systems or novel PIM-friendly applications, | This combined tutorial and workshop will focus on the latest advances in PIM technology, spanning both hardware and software. It will include novel PIM ideas, different tools and frameworks for conducting PIM research, and programming techniques and optimization strategies for PIM kernels. First, we will provide a series of lectures and invited talks that will provide an introduction to PIM, including an overview and a rigorous analysis of existing PIM hardware from industry and academia. Second, we will invite the broad PIM research community to submit and present their ongoing work on memory-centric systems. The program committee will favor papers that bring new insights on memory-centric systems or novel PIM-friendly applications, | ||
| - | **Time & Location**: March 30th, from 09:00 AM (CET) to 05:30P PM (CET) at the Penn Room II | + | **Time & Location**: March 30th, from 09:00 AM (CET) to 05:30P PM (CET) at the Penn Room II. |
| - | ==== Procedure for Selecting Presentations ==== | + | ==== Procedure for Selecting Presentations |
| This workshop consists of invited talks on the general topic of memory-centric computing systems. There are a limited number of slots for invited talks. If you would like to deliver a talk on related topics, please contact us by filling out [[https:// | This workshop consists of invited talks on the general topic of memory-centric computing systems. There are a limited number of slots for invited talks. If you would like to deliver a talk on related topics, please contact us by filling out [[https:// | ||
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| [[https:// | [[https:// | ||
| {{youtube> | {{youtube> | ||
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| ==== Organizers ==== | ==== Organizers ==== | ||
| ^ Name ^ E-mail ^ | ^ Name ^ E-mail ^ | ||
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| |[[https:// | |[[https:// | ||
| - | ===== Agenda | + | ===== Agenda |
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| - | ==== Workshop Materials ==== | + | |
| ^ Time ^ Speaker ^ Title ^ Materials ^ | ^ Time ^ Speaker ^ Title ^ Materials ^ | ||
| - | | 09: | + | | 09: |
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| - | | 09:30am-10:00am | + | |10:30am-11:00am |
| - | | 10:00am-10:30am | Geraldo F. Oliveira | Programming | + | |11:00am-11:30am | Geraldo F. Oliveira | Processing-Near-Memory Systems: Developments from Academia & Industry |
| - | | 10:30am-11:00am | N/A | Coffee Break | | | + | | 11:30am-12:00pm | Geraldo F. Oliveira | Processing-Using-Memory Systems for Bulk Bitwise Operations | {{geraldo-asplos25-lecture4-processing-using-memory-beforelecture.pdf|(PDF)}} {{geraldo-asplos25-lecture4-processing-using-memory-beforelecture.pptx|(PPT)}}| |
| - | | 11: | + | | 12:00am-12:30pm | Dr. Mohammad Sadr | Processing-Near-Storage & Processing-Using-Storage | {{mohammad-mcc-asplos-memorycentriccomputing-30-march-2025.pdf|(PDF)}} {{mohammad-mcc-asplos-memorycentriccomputing-30-march-2025.pptx|(PPT)}}| |
| - | | 11:30am-12:00pm | Dr, Mohammad Sadr | Processing-Near-Storage & Processing-Using-Storage | {{|(PDF)}} {{|(PPT)}}| | + | | 12: |
| - | | 12:00pm-12: | + | | 12: |
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| + | ==== Invited Speakers ==== | ||
| + | === Hamid Farzaneh (TU Dresden) === | ||
| + | **Talk Title:** CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms {{ :: | ||
| + | **Talk Abstract:** The rise of data-intensive applications exposed the limitations of conventional processor-centric von-Neumann architectures that struggle to meet the off-chip memory bandwidth demand. Therefore, recent innovations in computer architecture advocate compute-in-memory (CIM) and compute-near-memory (CNM), non-von- Neumann paradigms achieving orders-of-magnitude improvements in performance and energy consumption. Despite significant technological breakthroughs in the last few years, the programmability of these systems is still a serious challenge. Their programming models are too low-level and specific to particular system implementations. Since such future architectures are predicted to be highly heterogenous, | ||
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| + | **Bio:** [[https:// | ||
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| + | === Theocharis Diamantidis (National Technical University of Athens) === | ||
| + | **Talk Title:** Harnessing PIM Techniques for Accelerating Sum Operations in FPGA-DRAM Architectures | ||
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| + | **Talk Abstract:** In the current work, we present and evaluate a method to exploit circuits originally implemented for storage operations in memory arrays, such that we can perform logic and arithmetic operations inside commercial DRAM chips. That is to say, we explore techniques for performing bit-level calculations by relying exclusively on the analog properties inherent in memory arrays. We start by showing binary logic results, such as the AND/OR/NOT gates, which we then apply to multiple bits in sequential and parallel fashion. By combining distinct gate calculations, | ||
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| + | **Bio:** Theocharis Diamantidis is a current student at the National Technical University of Athens (NTUA) in the Department of Electrical and Computer Engineering where he now completes his Master thesis. He aspires to pursue a doctorate at the MicroLab laboratory at NTUA. His academic interests lie in circuit design and simulation, with a focus on Analog and Mixed-Signal Circuits and their applications. His master' | ||
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| + | === Krystian Chmielewski (Huawei Warsaw Research Center) === | ||
| + | **Talk Title:** Pitfalls of UPMEM Kernel Development | ||
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| + | **Talk Abstract:** Developing kernels for Processing-In-Memory (PIM) platforms presents unique challenges, particularly in data management and executing tasks concurrently on limited PIM processing units. While software development kits (SDKs) for PIM, such as the UPMEM SDK, provide essential tools for programmers, | ||
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| + | **Bio:** Krystian Chmielewski is a software engineer with 8 years of experience in emerging computing architectures and low-level performance optimizations. Since 2023, he has been working at Huawei Warsaw Research Center in Poland focusing on the enablement of novel Processing-In-Memory architectures and optimizing the JVM's just-in-time compiler. Prior to this, Krystian spent 6 years at Intel, where he specialized in compute runtimes and worked on features such as Mutable Command Lists. | ||
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| + | === Yintao He (UCAS) === | ||
| + | **Talk Title:** PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System {{ :: | ||
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| + | **Talk Abstract:** Large language models (LLMs) are widely used for natural language understanding and text generation. An LLM model relies on a time-consuming step called LLM decoding to generate output tokens. Several prior works focus on improving the performance of LLM decoding using parallelism techniques, such as batching and speculative decoding. State-of-the-art LLM decoding has both compute-bound and memory-bound kernels. Some prior works statically identify and map these different kernels to a heterogeneous architecture consisting of both processing-in-memory (PIM) units and computation-centric accelerators. We observe that characteristics of LLM decoding kernels (e.g., whether or not a kernel is memory-bound) can change dynamically due to parameter changes to meet user and/or system demands, making (1) static kernel mapping to PIM units and computation-centric accelerators suboptimal, and (2) one-size-fits-all approach of designing PIM units inefficient due to a large degree of heterogeneity even in memory-bound kernels. | ||
| + | In this paper, we aim to accelerate LLM decoding while considering the dynamically changing characteristics of the kernels involved. We propose PAPI (PArallel Decoding with PIM), a PIM-enabled heterogeneous architecture that exploits dynamic scheduling of compute-bound or memory-bound kernels to suitable hardware units. PAPI has two key mechanisms: (1) online kernel characterization to dynamically schedule kernels to the most suitable hardware units at runtime and (2) a PIM-enabled heterogeneous computing system that harmoniously orchestrates both computation-centric processing units and hybrid PIM units with different computing capabilities. Our experimental results on three broadly-used LLMs show that PAPI achieves 1.8× and 11.1× speedups over a state-of-the-art heterogeneous LLM accelerator and a state-of-the-art PIM-only LLM accelerator, | ||
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| + | **Bio:** Yintao He received the BE degree in electronic science and technology from Nankai University, Tianjin, China, in 2019. She is currently working toward the PhD degree with the University of Chinese Academy of Sciences, Beijing, China. Her research interests include processing in-memory and energy-efficient accelerators. | ||
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| + | === Yufeng Gu (University of Michigan) === | ||
| + | **Talk Title:** PIM Is All You Need: A CXL-Enabled GPU-Free System for Large Language Model Inference {{ :: | ||
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| + | **Talk Abstract:** Large Language Model (LLM) inference uses an autoregressive manner to generate one token at a time, which exhibits notably lower operational intensity compared to earlier Machine Learning (ML) models such as encoder-only transformers and Convolutional Neural Networks. At the same time, LLMs possess large parameter sizes and use key-value caches to store context information. Modern LLMs support context windows with up to 1 million tokens to generate versatile text, audio, and video content. A large key-value cache unique to each prompt requires a large memory capacity, limiting the inference batch size. Both low operational intensity and limited batch size necessitate a high memory bandwidth. However, contemporary hardware systems for ML model deployment, such as GPUs and TPUs, are primarily optimized for compute throughput. This mismatch challenges the efficient deployment of advanced LLMs and makes users to pay for expensive compute resources that are poorly utilized for the memory-bound LLM inference tasks. | ||
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| + | **Bio:** [[https:// | ||
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| + | === Dr. Christina Giannoula (University of Toronto) === | ||
| + | **Talk Title:** PyGim: An Efficient Graph Neural Network Library for Real Processing-In-Memory Architectures {{ :: | ||
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| + | **Talk Abstract:** Graph Neural Networks (GNNs) are emerging ML models to analyze graph-structure data. Graph Neural Network (GNN) execution involves both compute-intensive and memory-intensive kernels, the latter dominates the total time, being significantly bottlenecked by data movement between memory and processors. Processing-In-Memory (PIM) systems can alleviate this data movement bottleneck by placing simple processors near or inside to memory arrays. In this work, we introduce PyGim, an efficient ML library that accelerates GNNs on real PIM systems. We propose intelligent parallelization techniques for memory-intensive kernels of GNNs tailored for real PIM systems, and develop handy Python API for them. We provide hybrid GNN execution, in which the compute-intensive and memory-intensive kernels are executed in processor-centric and memory-centric computing systems, respectively. We extensively evaluate PyGim on a real-world PIM system with 1992 PIM cores using emerging GNN models, and demonstrate that it outperforms its state-of-the-art CPU counterpart on Intel Xeon by on average 3.04x, and achieves higher resource utilization than CPU and GPU systems. Our work provides useful recommendations for software, system and hardware designers. | ||
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| + | **Bio:** [[https:// | ||
| + | Engineering, | ||
| - | ==== Invited Speakers ==== | ||
| - | TBA | ||
| === Recommended Materials === | === Recommended Materials === | ||
start.1742898935.txt.gz · Last modified: 2025/03/25 10:35 by geraldod