ASPLOS 2026 Ramulator+DRAM Bender Tutorial

DRAM is predominantly used to build the main memory systems of modern computing devices. To improve performance, reliability, and security, it is critical to conduct both system-level simulation studies and experimental characterization of cutting-edge DRAM chips. Simulation enables understanding of the complex interactions between DRAM, emerging memory technologies, and modern applications, while real-chip characterization provides concrete insights into DRAM performance, robustness, latency, and power under different conditions (e.g., temperature and voltage).

This tutorial+workshop will introduce simulation-based DRAM research together with experimental DRAM characterization using real DRAM chips. Participants will gain practical experience with two widely used infrastructures in industry and academia: Ramulator, a cycle-accurate and extensible main memory simulator, and DRAM Bender, an FPGA-based DRAM testing infrastructure.

Ramulator is an extensible main memory simulator that provides cycle-level performance models for a variety of commercial DRAM standards (e.g., DDR3/4, LPDDR3/4, GDDR5, HBM), emerging memory technologies, and academic proposals. Its modular design enables easy integration of additional standards, technologies, and mechanisms. Ramulator is written in C++ and can be easily integrated into both full-system simulators, such as gem5, as well as other microarchitectural simulators, zsim, and Virtuoso.

DRAM Bender (based on SoftMC), is an FPGA-based DRAM testing infrastructure. DRAM Bender provides simple and intuitive high-level programming interfaces in C++ and Python. A user of DRAM Bender writes DRAM test programs in a high-level language. DRAM Bender’s programmer interface automatically translates these programs into low-level DRAM Bender instructions (e.g., DRAM commands, arithmetic, memory, control-flow instructions) on the FPGA. Thereby, DRAM Bender enables users with diverse technical backgrounds to rapidly characterize DRAM without requiring logic design expertise.

Time & Location: TBD.

YouTube livestream

TBD