3rd Ramulator & DRAM Bender Tutorial
Cutting-Edge Infrastructures
for Real and Future Memory System Evaluation
In conjunction with the ACM International Conference on Supercomputing 2026 (ICS 2026)
Belfast, Northern Ireland, United Kingdom
About
DRAM is predominantly used to build the main memory systems of modern computing devices. To improve performance, reliability, and security, it is critical to conduct both system-level simulation studies and experimental characterization of cutting-edge DRAM chips. Simulation enables understanding of the complex interactions between DRAM, emerging memory technologies, and modern applications, while real-chip characterization provides concrete insights into DRAM performance, robustness, latency, and power under different conditions (e.g., temperature and voltage).
This tutorial+workshop will introduce simulation-based DRAM research together with experimental DRAM characterization using real DRAM chips. We will provide an extensive overview of: Ramulator, a cycle-accurate and extensible main memory simulator, and DRAM Bender, an FPGA-based DRAM testing infrastructure.
Ramulator
Ramulator is an extensible main memory simulator that provides cycle-level performance models for a variety of commercial DRAM standards (e.g., DDR3/4, LPDDR3/4, GDDR5, HBM), emerging memory technologies, and academic proposals. Its modular design enables easy integration of additional standards, technologies, and mechanisms. Ramulator is written in C++ and can be easily integrated into both full-system simulators, such as gem5, as well as other microarchitectural simulators, zsim, and Virtuoso.
DRAM Bender
DRAM Bender (based on SoftMC), is an FPGA-based DRAM testing infrastructure. DRAM Bender provides simple and intuitive high-level programming interfaces in C++ and Python. A user of DRAM Bender writes DRAM test programs in a high-level language. DRAM Bender’s programmer interface automatically translates these programs into low-level DRAM Bender instructions (e.g., DRAM commands, arithmetic, memory, control-flow instructions) on the FPGA. Thereby, DRAM Bender enables users with diverse technical backgrounds to rapidly characterize DRAM without requiring logic design expertise.
Call for Papers
This workshop includes invited talks on DRAM characterization and memory system simulation using Ramulator and DRAM Bender.
We are soliciting extended abstracts to be included in the conference proceedings. Attendees interested in delivering a talk should submit a brief proposal with an extended abstract of their work (along with a brief bio). We invite submissions related to (but not limited to) the following topics:
Topics of Interest
We especially encourage early-stage research, work-in-progress results, experimental methodologies, and community contributions that will benefit researchers working with Ramulator or DRAM Bender.
Submission Guidelines
Questions about submissions? Contact nisa.bostanci@safari.ethz.ch or ataberk.olgun@safari.ethz.ch.
Tentative Agenda
| Time | Duration | Speaker | Title | Materials |
|---|---|---|---|---|
| 09:00-09:05 | 5 min | Ataberk Olgun | Logistics | |
| 09:05-09:50 | 45 min | Onur Mutlu | Tools for Evaluating Memory and Memory-Centric Computing DRAM, Storage, Virtual Memory | Download |
| 09:50-10:30 | 40 min | Ataberk Olgun | DRAM Bender (Introduction + Research Highlights) | Download |
| Time | Duration | Speaker | Title | Materials |
|---|---|---|---|---|
| 11:00-11:20 | 20 min | Antonino Tumeo | Realistic DRAM Timing for HLS: Closing the Memory Fidelity Gap with Ramulator-Backed Co-Simulation | Download |
| 11:20-11:50 | 30 min | Haocong Luo | Introduction to Ramulator and Memory System Simulation | |
| 11:50-12:30 | 40 min | Haocong Luo | Deep Dive into Ramulator 2.1 |
Invited Speakers
High-Level Synthesis (HLS) tools typically model off-chip memory using fixed-latency stubs, masking the dominant performance factors of real DRAM systems - row activations, bank conflicts, scheduling effects, and refresh interference. This memory fidelity gap causes cycle estimates to deviate by 1.5-2.5x on common compute kernels and by nearly 2x on parallel graph workloads, often misleading design-space exploration and delaying memory-sensitive decisions until FPGA deployment.
We present a cycle-accurate DRAM co-simulation framework that replaces Bambu's fixed-latency memory backend with Ramulator-2.0 through a protocol-faithful AXI4 bridge. Our design introduces a non-blocking request/completion interface, tag-preserving out-of-order response handling, and bidirectional back-pressure control, all integrated through SystemVerilog DPI-C and IPC layers without modifying upstream HLS flow. The combined system preserves functional correctness while exposing realistic DRAM timing and concurrency behavior.
Evaluated on 13 PolyBench kernels, multiple MachSuite workloads, and SPARTA-generated multi-threaded graph accelerators targeting a Xilinx Alveo U250 and a matched DDR4-2400R model, our co-simulation reveals that fixed-delay models either substantially under-predict or over-predict runtime - and that no single scalar delay can match true DRAM behavior across kernels or parallelism levels. Under maximum spatial x temporal parallelism, fixed-delay models converge to nearly identical results yet remain approximately 2x too optimistic, exposing structural memory-system effects (controller queuing, bank conflicts, refresh contention) that simple per-access constants cannot capture.
Our results demonstrate that realistic DRAM timing is essential for trustworthy HLS performance estimation, and that cycle-accurate memory co-simulation can replace many costly FPGA iterations during accelerator design.
Dr. Antonino Tumeo received an MS degree in Informatic Engineering (2005) and a PhD in Computer Engineering (2009) from Politecnico di Milano in Italy. Since February 2011, he has been a research scientist in Pacific Northwest National Laboratory's (PNNL) Future Computing Technologies group. He joined PNNL in 2009 as a post-doctoral research associate. Previously, he was a post-doctoral researcher at Politecnico di Milano. His research focuses on custom systems for graph analytics, electronic design automation (including high-level synthesis), and in general hardware specialization, fostering the creation of an open hardware design ecosystem. Recently, he also started research in the area of analog computing, specifically focusing on chemical computing.
Livestream
🔴 Can't attend in person? Join us live!
The tutorial will be livestreamed on YouTube. A replay will also be available afterwards.
▶️ Watch on YouTubeOrganizers
F. Nisa Bostanci
F. Nisa Bostanci is a 4th-year PhD student in the SAFARI Research Group at ETH Zurich, under the supervision of Prof. Onur Mutlu. She is broadly interested in computer architecture and, more specifically, in security, reliability, and safety (robustness) of memory systems, emerging memory and computation paradigms, including Processing-In-Memory architectures (PIM), and designing effective and efficient solutions to address robustness issues in modern and future systems. Her recent works uncover and mitigate new security vulnerabilities that emerge with the adoption of read disturbance solutions and PIM architectures to aid in designing robust future systems.
Ataberk Olgun
Ataberk Olgun is a senior PhD student at ETH Zurich, working with Prof. Onur Mutlu. His broad research interests include designing secure, high-performance, and energy-efficient DRAM architectures. Especially with the worsening RowHammer vulnerability, it is increasingly difficult to design new DRAM architectures that satisfy all three characteristics. His current research focuses on i) deeply understanding and ii) efficiently mitigating the RowHammer vulnerability in modern systems.
Haocong Luo
Haocong Luo is a PhD student in the SAFARI Research Group at ETH Zurich under the supervision of Prof.Onur Mutlu. His current broader research interests are 1) understanding and improving the performance and reliability of DRAM-based memory systems, 2) accelerating BVH traversals to enable high-performance path-traced rendering algorithms, and 3) designing efficient memory architectures and systems for Large Language Models.
Ismail Emir Yuksel
Ismail Emir Yuksel is a 2nd-year PhD student in the SAFARI Research Group at ETH Zurich under the supervision of Prof. Onur Mutlu. His current broader research interests are in computer architecture, processing-in-memory, and hardware security, focusing on understanding, enhancing, and exploiting fundamental computational capabilities of modern DRAM architectures. His recent publications show that commodity DRAM chips, without any modification to the chip itself (only with modifications to the memory controller), are able to execute bulk-bitwise computation and data movement operations (including NAND, NOR, NOT, AND, OR, MAJority, multi-row copy, and initialization functions) in a reasonably robust manner.
Professor Onur Mutlu
Onur Mutlu is a Professor of Computer Science at ETH Zurich. He previously held the William D. and Nancy W. Strecker Early Career Professorship at Carnegie Mellon University. His research interests are in computer architecture, computing systems, hardware security, memory & storage systems, and bioinformatics, with a major focus on designing fundamentally energy-efficient, high-performance, and robust computing systems. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held product, research and visiting positions at Intel Corporation, Advanced Micro Devices, VMware, Google, and Stanford University. He received various honors for his research, including the 2025 IEEE Computer Society Harry H. Goode Memorial Award “for seminal contributions to computer architecture research and practice, especially in memory systems.” He is an ACM Fellow, IEEE Fellow, and an elected member of the Academy of Europe. He enjoys teaching, mentoring, and enabling & democratizing access to high-quality research and education. He has supervised 25 PhD graduates, many of whom received major dissertation awards, 18 postdoctoral trainees, and more than 70 Master’s and Bachelor’s students. His computer architecture and digital logic design course lectures and materials are freely available on YouTube and his research group makes a wide variety of artifacts freely available online. For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.
Event Location
Venue
Assembly Buildings Conference Centre
2-10 Fisherwick Place
Belfast, BT1 6DW
Northern Ireland, United Kingdom
The tutorial will be held in conjunction with ICS 2026.
For registration and accommodation information, please visit the ICS 2026 website.
Contact
For questions about the tutorial, please contact the organizers:
General Inquiries: nisa.bostanci@safari.ethz.ch and ataberk.olgun@safari.ethz.ch
SAFARI Research Group: safari.ethz.ch