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--- start [2025/06/18 20:17] – [Workshop Description] geraldod
+++ start [2025/06/21 08:15] (current) – iyueksel
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 This combined tutorial and workshop will focus on the latest advances in PIM technology, spanning both hardware and software. It will include novel PIM ideas, different tools and frameworks for conducting PIM research, and programming techniques and optimization strategies for PIM kernels. First, we will provide a series of lectures and invited talks that will provide an introduction to PIM, including an overview and a rigorous analysis of existing PIM hardware from industry and academia. Second, we will invite the broad PIM research community to submit and present their ongoing work on memory-centric systems. The program committee will favor papers that bring new insights on memory-centric systems or novel PIM-friendly applications, address key system integration challenges in academic or industry PIM architectures, or put forward controversial points of view on the memory-centric execution paradigm. We also consider position papers, especially from industry, that outline design and process challenges affecting PIM systems, new PIM architectures, or system solutions for real state-of-the-art PIM devices.
-Time & Location: June 21st, from 02:00 PM (JST) to 05:45 PM (JST) at room 26-B1F (Building 26, Room B1).
+Time & Location: June 21st, from 02:00 PM (JST) to 06:15 PM (JST) at room 26-B1F (Building 26, Room B1).
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 |[[https://people.inf.ethz.ch/omutlu/index.html|Professor Onur Mutlu]]| <onur.mutlu@safari.ethz.ch> |
-===== Agenda =====
+===== Agenda & Workshop Materials =====
-==== Tutorial Materials ====
+^ Time ^ Speaker ^ Title ^ Materials ^
+| 02:00pm-02:05pm  | Dr. Geraldo F. Oliveira | Logistics |{{geraldo-isca25-lecture0-introduction-beforelecture.pdf|(PDF)}} {{geraldo-isca25-lecture0-introduction-beforelecture.pptx|(PPT)}}|
+| 02:05pm-03:00pm   | Prof. Onur Mutlu | Memory-Centric Computing |{{ onur-mccsys-memorycentriccomputing-21-june-2025.pdf|(PDF)}} {{onur-mccsys-memorycentriccomputing-21-june-2025.pptx|(PPT)}}|
+| 03:00pm-03:30pm   | [[https://research.ibm.com/people/alper-buyuktosunoglu|Dr. Alper Buyuktosunoglu]] | A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications | {{|(PDF)}} {{|(PPT)}}|
+| 03:30pm-03:45pm   | N/A | **Coffee Break** | |
+| 03:45pm-04:15pm   | Dr. Geraldo F. Oliveira | Processing-Using-Memory Systems for Bulk Bitwise Operations | {{geraldo-isca25-lecture2-processing-using-memory-beforelecture.pdf|(PDF)}} {{geraldo-isca25-lecture2-processing-using-memory-beforelecture.pptx|(PPT)}}|
+| 04:15pm-04:45pm  | [[https://scholar.google.com/citations?user=qfK90PkAAAAJ| Ismail Emir Yüksel]] | PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips | {{ismail_pudhammer_isca25_18jun.pdf|(PDF)}} {{isca25_mccsys_ismail_talk.pptx|(Px)}}  {{ismail_pudhammer_isca25_18jun.pptx|(PPT)}}|
+| 04:45pm-05:15pm  | Dr. Geraldo F. Oliveira | Processing-Near-Memory Architectures: Developments from Industry & Academia | {{geraldo-isca25-lecture3-processing-near-memory-beforelecture.pdf|(PDF)}} {{geraldo-isca25-lecture3-processing-near-memory-beforelecture.pptx|(PPT)}}|
+| 05:15pm-05:45pm   | Manos Frouzakis | PIMDAL: Mitigating the Memory Bottleneck in Data Analytics using a Real Processing-in-Memory System | {{pimdal_isca.pdf|(PDF)}} {{pimdal_isca.pptx|(PPT)}}|
+| 05:45pm-06:15pm   | Dr. Mohammad Sadr | Processing-Near-Storage & Processing-Using-Storage | {{mohammad-mcc-isca-memorycentriccomputing-21-june-2025.pdf|(PDF)}} {{mohammad-mcc-isca-memorycentriccomputing-21-june-2025.pptx|(PPT)}}|
-TBA
 ==== Invited Speakers ====
-TBA
+=== Alper Buyuktosunoglu (IBM Research) ===
+**Talk Title:** A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications {{ ::alper_headshot.png?nolink&200|}}
+**Talk Abstract:** Fully homomorphic encryption (FHE) is a powerful cryptographic technique that enables computation on encrypted data without needing to decrypt it. FHE applications are both compute- and memory-intensive, owing to expensive operations on large data. Hierarchical near-DRAM processing (NDP) solution for FHE applications, harnesses the massive DRAM bank bandwidth. We observe various data access patterns in FHE that reveal distinct levels of parallelism: element-wise, limb-wise, coefficient-wise, and ciphertext-wise. We will discuss an NDP solution that exploits these levels of parallelism to map FHE operations and data onto different hierarchies of the NDP, while addressing major challenges with NDP for FHE.
+**Bio:** [[https://research.ibm.com/people/alper-buyuktosunoglu|Alper Buyuktosunoglu]] received PhD degree in electrical and computer engineering from University of Rochester. Currently, he is a Principal Research Scientist in Efficient and Resilient Systems department at IBM T. J. Watson Research Center. He has been involved in research and development work in support of IBM z Systems and IBM POWER Systems in the areas of computer architecture and robust power management. He has over 200 patents, has received several IBM-internal awards, IEEE Micro Top Pick recognition, has published over 140 papers, and has served on various conference technical program committees in these areas. He also has served on the editorial board of IEEE MICRO. Dr. Buyuktosunoglu is a member of the IBM Academy of Technology, Hall-of-fame of MICRO, Hall-of-fame of HPCA, an IBM Master Inventor and an IEEE Fellow.
 === Recommended Materials ===