ISCA 2025 Memory Centric Workshop

Processing-in-Memory (PIM) is a computing paradigm that aims to overcome data movement bottlenecks by making memory systems compute-capable. Explored over several decades since the 1960s, PIM systems are now becoming a reality with the advent of the first commercial products and prototypes. PIM can improve performance and energy efficiency for many modern applications. However, there are many open questions spanning the entire computing stack and many challenges for widespread adoption.

This combined tutorial and workshop will focus on the latest advances in PIM technology, spanning both hardware and software. It will include novel PIM ideas, different tools and frameworks for conducting PIM research, and programming techniques and optimization strategies for PIM kernels. First, we will provide a series of lectures and invited talks that will provide an introduction to PIM, including an overview and a rigorous analysis of existing PIM hardware from industry and academia. Second, we will invite the broad PIM research community to submit and present their ongoing work on memory-centric systems. The program committee will favor papers that bring new insights on memory-centric systems or novel PIM-friendly applications, address key system integration challenges in academic or industry PIM architectures, or put forward controversial points of view on the memory-centric execution paradigm. We also consider position papers, especially from industry, that outline design and process challenges affecting PIM systems, new PIM architectures, or system solutions for real state-of-the-art PIM devices.

Submissions must be original, unpublished work and not under consideration at another conference or journal. The authors must use the MCCSys hotcrp to submit their papers. Papers must be formatted for US letter (not A4) size paper using the Microsoft Word or LaTeX templates provided on the IEEE website. The length of the submitted papers should be 5 pages at maximum, excluding references. Appendices count towards the page limit, while the main body of the paper should be self-contained. Paper submissions will go through a double-blind reviewing process by the MCCSys program committee and should not include author names or affiliations. At least one author for each accepted paper is required to present the paper at the workshop.

We expect that at least some papers at MCCSys would represent “work-in-progress” projects. Therefore, authors of published papers could choose to extend their work to full-length conference papers later.

Talk Title: Architectures and Programming Models for General-Purpose Near-Data Computing

Talk Abstract: As computer systems are increasingly bottlenecked by data movement, traditional CPU scaling can no longer meet processing demands. To continue improving performance and energy efficiency, novel data-centric architectures move compute closer to data, typically by adding compute resources near data storage. Although these near-data computing (NDC) architectures promise significant gains in performance and energy efficiency, they are often limited by targeting a narrow range of application domains. In this talk, we present two architectures, täkō and Leviathan, that generalize NDC by adding programmable compute resources within the memory hierarchy and providing flexible, easy-to-use programming interfaces. By enabling architectures to implement a wide range of data-centric optimizations, täkō and Leviathan provide a path toward practical NDC.

Bio: Brian Schwedock is an SoC architect at Samsung SARC/ACL. He earned his PhD in Electrical and Computer Engineering at Carnegie Mellon University in 2023. His research tackles the ever-growing data-movement challenge by introducing programmable, data-centric architectures. He currently develops the memory-hierarchy architecture for Samsung’s Exynos SoCs.

Talk Title: System Software and Libraries for Sparse Computational Kernels in PIM Architectures

Talk Abstract: Processing-In-Memory (PIM) offers a promising solution to alleviate the data movement bottleneck between memory and processors. Several manufacturers have already started to commercialize PIM architectures, providing significant performance and energy improvements for memory-intensive workloads. This talk will explore how specialized libraries and system software can unlock the potential of PIM architectures. I will first present SparseP, the first comprehensive Sparse Matrix Vector Multiplication (SpMV) library for real-world PIM systems. SparseP explores various parallelization strategies, load balancing, and synchronization techniques across thousands of PIM cores, offering insights into performance and energy efficiency benefits. Then, I will briefly introduce PyGim, a novel Graph Neural Network (GNN) library tailored for PIM systems, which optimizes memory-intensive GNN kernels through intelligent parallelization strategies. Our evaluations demonstrate that PyGim provides significant performance and energy improvements over prior state-of-the-art approaches.

Bio: Christina Giannoula received the Ph.D. degree from the School of Electrical and Computer Engineering, National Technical University of Athens, advised by Prof. Georgios Goumas, Prof. Nectarios Koziris, and Prof. Onur Mutlu, in October 2022. She is currently a Postdoctoral Researcher with the University of Toronto working with Prof. Gennady Pekhimenko and his research group. She is also with the SAFARI Research Group and Prof. Onur Mutlu. Her research interests include the intersection of computer architecture, computer systems, and high-performance computing. Specifically, her research focuses on the hardware/software co-design of emerging applications, including graph processing, pointer-chasing data structures, machine learning workloads, and sparse linear algebra, with modern computing paradigms, such as large-scale multicore systems, disaggregated memory systems, and near-data processing architectures. She has several publications and awards for her research on the aforementioned topics. She is a member of ACM, ACM-W, and the Technical Chamber of Greece.

• Mutlu, O., Ghose, S., Gómez-Luna, J., and Ausavarungnirun, R., “A Modern Primer on Processing in Memory.” In Emerging Computing: From Devices to Systems, 2023.
  • PDF (arXiv)
• Gómez-Luna, J., El Hajj, I., Fernandez, I., Giannoula, C., Oliveira, G. F., and Mutlu, O., “Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System.” IEEE Access, 2022.
  • PDF (arXiv)
  • Repository (GitHub)
• Giannoula, C., Fernandez, I., Gómez-Luna, J., Koziris, N., Goumas, G., and Mutlu, O., “SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures,” in SIGMETRICS 2022.
  • PDF (arXiv)
  • Repository (GitHub)
• Olgun, A., Gómez-Luna, J., Kanellopoulos, K., Salami, B., Hassan, H., Ergin, O., and Mutlu, O., “PiDRAM: A Holistic End-to-End FPGA-Based Framework for Processing-in-DRAM.” ACM TACO, 2022.
  • PDF (arXiv)
  • Repository (GitHub)
• Oliveira, G. F., Gómez-Luna, J., Orosa, L., Ghose, S., Vijaykumar, N., Fernandez, I., Sadrosadati, M., Mutlu, O., “DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks.” IEEE Access, 2021.
  • PDF (arXiv)
  • Repository (GitHub)
• Luo, H., Tu, Y. C., Bostancı, F. N., Olgun, A., Ya, A. G., Mutlu, O., “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator.” IEEE CAL, 2023.
  • PDF (arXiv)
  • Repository (GitHub)
• Olgun, A., Hassan, H., Yağlıkçı, A. G., Tuğrul, Y. C., Orosa, L., Luo, H., Patel, M., Ergin, O., Mutlu, O., “DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips.” IEEE CAD, 2023.
  • PDF (arXiv)
  • Repository (GitHub)
• Oliveira, G. F., Olgun, A., Yaglikci, A. G., Bostanci, N., Gomez-Luna, J., Ghose, S., Mutlu, O., “MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing,” in HPCA, 2024.
  • PDF (arXiv)
  • Repository (GitHub)
• Hajinazar, N., Oliveira, G. F., Gregorio, S., Ferreira, J. D., Ghiasi, N. M., Patel, M., Alser, M., Ghose, S., Gomez-Luna, J., Mutlu. O., “SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM,” in ASPLOS, 2021.
  • PDF (arXiv)
  • Full Talk Video
• Seshadri, V., Lee, D., Mullins, T., Hassan, H., Boroumand, A., Kim, J., Kozuch, M. A., Mutlu, O., Gibbons, P. B., Mowry, T. C., “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” in MICRO, 2017.
  • PDF
• Schwedock, B.C., Yoovidhya, P., Seibert, J. and Beckmann, N., “Täkō: A Polymorphic Cache Hierarchy for General-Purpose Optimization of Data Movement,” in ISCA, 2022.
  • PDF
• Schwedock, B.C. and Beckmann, N., “Leviathan: A Unified System for General-Purpose Near-Data Computing,” in MICRO, 2024.
  • PDF

• Mutlu O., Memory-Centric Computing (IMACAW Keynote Talk at DAC 2023), July 2023:
  • PDF PPT Video
• Processing-in-Memory: A Workload-Driven Perspective (summary paper about recent research in PIM):
  • PDF
• Processing Data Where It Makes Sense: Enabling In-Memory Computation (summary paper about recent research in PIM):
  • PDF
• Processing-in-Memory course (Spring 2022):
  • Course website
• Gómez-Luna, J., and Mutlu, O., Data-Centric Architectures: Fundamentally Improving Performance and Energy (227-0085-37L), ETH Zürich, Fall 2022.
  • Course Website
  • Lecture Playlist
  • PDF (arXiv)