2nd Ramulator & DRAM Bender Tutorial

For years, our research group focused on developing and maintaining custom, in-house performance simulators for main-memory exploration. Recently, however, the infrastructure landscape has shifted. Today, our research relies mostly on widely adopted open-source tools: Ramulator for architectural simulation and DRAM-Bender for characterizing real-world DRAM hardware. In this talk, I will discuss the rationale behind this transition, the practical implications for academic research groups, and our perspectives on the future of memory system evaluation infrastructure.

Jung Ho Ahn is a Professor at Seoul National University. He received his Ph.D. in Electrical Engineering from Stanford University in 2007. Prior to joining SNU, he was a Senior Research Scientist at HP Labs, and he later completed a sabbatical at Google and Samsung Electronics. His research focuses on bridging the gap between the performance and efficiency demands of emerging applications and the potential of modern massively parallel systems, with a specific emphasis on memory subsystems. Professor Ahn is an inductee of the HPCA, ISCA, and MICRO Halls of Fame.

Cryogenic operation has been proposed as a potential approach to alleviate DRAM power and bandwidth limitations at room temperature, but its impact across the full memory stack remains unclear. In this talk, I will present our recent full-stack evaluation of cryogenic DRAM, spanning device-level characterization, circuit-level simulation, and DIMM-level testing of commercial DDR4 modules. Temperature-dependent measurements on representative sub-20 nm DRAM devices show strongly suppressed leakage and improved switching behavior at low temperature, while circuit simulations indicate substantial power–performance opportunities for DRAM peripheral circuits at 77 K. At the DIMM level, we examine functional operating limits, data retention, RowHammer vulnerability, operating frequency, and power consumption under cryogenic conditions. Our results show that although retention can be significantly improved at low temperature, RowHammer remains strongly pattern-dependent and can constrain the usable refresh margin. In addition, DIMM-level dynamic power does not automatically improve without voltage or circuit optimization. These findings highlight the need for coordinated device–circuit–system co-optimization to realize functional, reliable, and energy-efficient cryogenic DRAM. Through this case study, I will introduce how DRAM Bender enables fine-grained DIMM-level characterization by allowing direct control over DRAM commands, timing parameters, refresh behavior, and stress patterns.

Acknowledgement: I would like to acknowledge Prof. Jungsik Kim and his group at Gyeongsang National University for their ongoing collaboration on DRAM characterization and reliability under extreme operating environments.

Dr. Zhaoqiang Bai is a Senior Research Manager at Beijing Superstring Academy of Memory Technology, where he works on advanced memory pathfinding, including 3D-DRAM, cryogenic DRAM, and non-volatile memory technologies. His research interests include advanced memory materials/device modeling, and the reliability and characterization of memories under extreme environments. Dr. Bai received his Ph.D. in Physics from the National University of Singapore; he also holds an M.S. in Electrical Engineering from Stanford University. He has published more than 30 research papers and filed more than 20 patent applications.

Ramulator is one of the most widely used cycle-accurate DRAM simulators in computer-architecture research, valued for its speed, modularity, and broad standard coverage. This talk asks how the simulator itself can be improved, and presents a roadmap organized around three areas. The first area is modeling fidelity and policy completeness: extending Ramulator with controller and DRAM behaviors that are missing or only partially supported — state-of-the-art address mappings such as those used by recent Intel and AMD Zen processors, more row-buffer (page) policies, same-bank refresh and refresh management, and a broader set of schedulers. The second area is integration with more accurate front-end simulators, such as gem5 and ChampSim, providing detailed, maintained wrappers or tighter built-in coupling so that memory-system performance can be measured under a realistic, detailed microarchitecture — capturing the effects of branch prediction, prefetching, and the cache hierarchy. The third area is security and reliability: as these research topics grow in importance, first-class support such as built-in RowHammer test patterns and ECC error-injection modeling would let users study these effects directly. Together these changes make Ramulator a more complete, better-integrated, and more broadly useful platform.

Prashant J. Nair is an Associate Professor at the University of British Columbia (UBC) and also the lead architect of the 3D-memory architecture at d-Matrix. He leads the Systems and Architectures (STAR) Lab at UBC and is also an Affiliate Fellow of the Quantum Algorithms Institute. His research focuses on memory architectures and systems. Dr. Nair’s recognitions include the 2024 TCCA Young Architect Award, the 2025 DSN Test of Time Award, the HPCA 2023 Best Paper Award, a MICRO 2024 Best Paper nomination, and the HPCA 2025 Distinguished Artifact Award. Over the past decade, he has published more than 40 papers in top-tier venues. Prior to his promotion to Associate Professor, as an Assistant Professor, he was inducted into all three halls of fame of computer architecture: ISCA, MICRO, and HPCA.