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| ^ Time ^ Speaker ^ Title ^ Materials ^ | ^ Time ^ Speaker ^ Title ^ Materials ^ |
| | 01:00pm-01:30pm | Prof. Onur Mutlu / Geraldo F. Oliveira | Memory-Centric Computing |{{|(PDF)}} {{|(PPT)}}| | | 01:00pm-01:30pm | Prof. Onur Mutlu / Geraldo F. Oliveira | Memory-Centric Computing |{{geraldo-micro24-lecture1-memory-centric-computing-beforelecture.pdf|(PDF)}} {{geraldo-micro24-lecture1-memory-centric-computing-beforelecture.pptx|(PPT)}}| |
| | 01:30pm-02:00pm | Geraldo F. Oliveira | Processing-Near-Memory Systems: Academia & Industry Developments | {{|(PDF)}} {{|(PPT)}}| | | 01:30pm-02:00pm | Geraldo F. Oliveira | Processing-Near-Memory Systems: Developments fro Academia & Industry | {{geraldo-micro24-lecture2-processing-near-memory-beforelecture.pdf|(PDF)}} {{geraldo-micro24-lecture2-processing-near-memory-beforelecture.pptx|(PPT)}}| |
| | 02:00pm-02:30pm | Dr. Brian Schwedock | Architectures and Programming Models for General-Purpose Near-Data Computing | {{|(PDF)}} {{|(PPT)}}| | | 02:00pm-02:30pm | [[https://brian-schwedock.github.io/|Dr. Brian Schwedock]] | Architectures and Programming Models for General-Purpose Near-Data Computing | {{2024.pim-micro.ndc.pdf|(PDF)}} {{2024.pim-micro.ndc.pptx|(PPT)}}| |
| | 02:30pm-03:00pm | Dr. Christina Giannoula | System Software and Libraries for Sparse Computational Kernels in PIM Architectures |{{|(PDF)}} {{|(PPT)}}| | | 02:30pm-03:00pm | Geraldo F. Oliveira | Processing-Using-Memory Systems for Bulk Bitwise Operations |{{geraldo-micro24-lecture3-processing-using-memory-beforelecture.pdf|(PDF)}} {{geraldo-micro24-lecture3-processing-using-memory-beforelecture.pptx|(PPT)}}| |
| | 03:00pm-03:30pm | N/A | Coffee Break | | | | 03:00pm-03:30pm | N/A | Coffee Break | | |
| | 03:30pm-03:30pm | Geraldo F. Oliveira | Processing-Using-Memory Systems for Bulk Bitwise Operations |{{|(PDF)}} {{|(PPT)}}| | | 03:30pm-04:00pm | Ataberk Olgun | Infrastructure for Processing-Using-Memory Research |{{2024_micro_pim_tutorial_dram_pum_infrastructure.pdf|(PDF)}} {{2024_micro_pim_tutorial_dram_pum_infrastructure.pptx|(PPT)}}| |
| | 04:00pm-04:30pm | Ataberk Olgun | Infrastructure for Processing-Using-Memory Research | {{|(PDF)}} {{|(PPT)}}| | | 04:00pm-04:30pm | [[https://cgiannoula.github.io/|Dr. Christina Giannoula]] | System Software and Libraries for Sparse Computational Kernels in PIM Architectures | {{sparselibraries_pim.pdf|(PDF)}} {{sparselibraries_pim.pptx|(PPT)}}| |
| | 04:30pm-05:30pm | Nika Mansouri Ghiasi | Storage-Centric Computing for Genomics and Metagenomics |{{|(PDF)}} {{|(PPT)}}| | | 04:30pm-05:00pm | Nika Mansouri Ghiasi | Storage-Centric Computing for Genomics and Metagenomics |{{pim-tutorial-micro24-nika-v2.pdf|(PDF)}} {{pim-tutorial-micro24-nika-v2.pptx|(PPT)}}| |
| | 05:00pm | Geraldo F. Oliveira | Research Challenges for PIM & Closing Remarks |{{|(PDF)}} {{|(PPT)}}| | | 05:00pm | Geraldo F. Oliveira | Research Challenges for PIM & Closing Remarks |{{geraldo-micro24-lecture4-adoption-programmability-beforelecture.pdf|(PDF)}} {{geraldo-micro24-lecture4-adoption-programmability-beforelecture.pptx|(PPT)}}| |
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| ==== Invited Speakers ==== | ==== Invited Speakers ==== |
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| === Dr. Brian C. Schwedock === | === Dr. Brian C. Schwedock === |
| * Talk Tile: Architectures and Programming Models for General-Purpose Near-Data Computing | **Talk Title:** Architectures and Programming Models for General-Purpose Near-Data Computing{{ ::brian_headshot.jpg?nolink&200|}} |
| * Talk Abstract: As computer systems are increasingly bottlenecked by data movement, traditional CPU scaling can no longer meet processing demands. To continue improving performance and energy efficiency, novel data-centric architectures move compute closer to data, typically by adding compute resources near data storage. Although these near-data computing (NDC) architectures promise significant gains in performance and energy efficiency, they are often limited by targeting a narrow range of application domains. In this talk, we present two architectures, täkō and Leviathan, that generalize NDC by adding programmable compute resources within the memory hierarchy and providing flexible, easy-to-use programming interfaces. By enabling architectures to implement a wide range of data-centric optimizations, täkō and Leviathan provide a path toward practical NDC. | |
| * Bio: Brian Schwedock is an SoC architect at Samsung SARC/ACL. He earned his PhD in Electrical and Computer Engineering at Carnegie Mellon University in 2023. His research tackles the ever-growing data-movement challenge by introducing programmable, data-centric architectures. He currently develops the memory-hierarchy architecture for Samsung’s Exynos SoCs. | **Talk Abstract:** As computer systems are increasingly bottlenecked by data movement, traditional CPU scaling can no longer meet processing demands. To continue improving performance and energy efficiency, novel data-centric architectures move compute closer to data, typically by adding compute resources near data storage. Although these near-data computing (NDC) architectures promise significant gains in performance and energy efficiency, they are often limited by targeting a narrow range of application domains. In this talk, we present two architectures, täkō and Leviathan, that generalize NDC by adding programmable compute resources within the memory hierarchy and providing flexible, easy-to-use programming interfaces. By enabling architectures to implement a wide range of data-centric optimizations, täkō and Leviathan provide a path toward practical NDC. |
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| | **Bio:** [[https://brian-schwedock.github.io/#myPage|Brian Schwedock]] is an SoC architect at Samsung SARC/ACL. He earned his PhD in Electrical and Computer Engineering at Carnegie Mellon University in 2023. His research tackles the ever-growing data-movement challenge by introducing programmable, data-centric architectures. He currently develops the memory-hierarchy architecture for Samsung’s Exynos SoCs. |
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| | === Dr. Christina Giannoula === |
| | **Talk Title:** System Software and Libraries for Sparse Computational Kernels in PIM Architectures{{ ::christina_headshot.jpg?nolink&200|}} |
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| | **Talk Abstract:** Processing-In-Memory (PIM) offers a promising solution to alleviate the data movement bottleneck between memory and processors. Several manufacturers have already started to commercialize PIM architectures, providing significant performance and energy improvements for memory-intensive workloads. This talk will explore how specialized libraries and system software can unlock the potential of PIM architectures. I will first present SparseP, the first comprehensive Sparse Matrix Vector Multiplication (SpMV) library for real-world PIM systems. SparseP explores various parallelization strategies, load balancing, and synchronization techniques across thousands of PIM cores, offering insights into performance and energy efficiency benefits. Then, I will briefly introduce PyGim, a novel Graph Neural Network (GNN) library tailored for PIM systems, which optimizes memory-intensive GNN kernels through intelligent parallelization strategies. Our evaluations demonstrate that PyGim provides significant performance and energy improvements over prior state-of-the-art approaches. |
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| | **Bio:** [[https://cgiannoula.github.io/#home|Christina Giannoula]] received the Ph.D. degree from the School of Electrical and Computer |
| | Engineering, National Technical University of Athens, advised by Prof. Georgios Goumas, Prof. Nectarios Koziris, and Prof. Onur Mutlu, in October 2022. She is currently a Postdoctoral Researcher with the University of Toronto working with Prof. Gennady Pekhimenko and his research group. She is also with the SAFARI Research Group and Prof. Onur Mutlu. Her research interests include the intersection of computer architecture, computer systems, and high-performance computing. Specifically, her research focuses on the hardware/software co-design of emerging applications, including graph processing, pointer-chasing data structures, machine learning workloads, and sparse linear algebra, with modern computing paradigms, such as large-scale multicore systems, disaggregated memory systems, and near-data processing architectures. She has several publications and awards for her research on the aforementioned topics. She is a member of ACM, ACM-W, and the Technical Chamber of Greece. |
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| ==== Learning Materials ==== | ==== Learning Materials ==== |
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| === Recommended Materials === | === Recommended Materials === |
| * Mutlu, O., Ghose, S., Gómez-Luna, J., and Ausavarungnirun, R. A Modern Primer on Processing in Memory. In Emerging Computing: From Devices to Systems, 2023. | * Mutlu, O., Ghose, S., Gómez-Luna, J., and Ausavarungnirun, R., "//A Modern Primer on Processing in Memory//." In Emerging Computing: From Devices to Systems, 2023. |
| * Gómez-Luna, J., El Hajj, I., Fernandez, I., Giannoula, C., Oliveira, G. F., and Mutlu, O. Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System. IEEE Access, 2022. | * [[https://arxiv.org/pdf/2012.03112 | PDF (arXiv)]] |
| | * Gómez-Luna, J., El Hajj, I., Fernandez, I., Giannoula, C., Oliveira, G. F., and Mutlu, O., "//Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System//." IEEE Access, 2022. |
| * [[https://arxiv.org/pdf/2105.03814.pdf | PDF (arXiv)]] | * [[https://arxiv.org/pdf/2105.03814.pdf | PDF (arXiv)]] |
| * [[https://github.com/CMU-SAFARI/prim-benchmarks | Repository (GitHub)]] | * [[https://github.com/CMU-SAFARI/prim-benchmarks | Repository (GitHub)]] |
| * Giannoula, C., Fernandez, I., Gómez-Luna, J., Koziris, N., Goumas, G., and Mutlu, O. SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures. SIGMETRICS 2022. | * Giannoula, C., Fernandez, I., Gómez-Luna, J., Koziris, N., Goumas, G., and Mutlu, O., "//SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures//," in SIGMETRICS 2022. |
| * [[https://arxiv.org/pdf/2201.05072.pdf | PDF (arXiv)]] | * [[https://arxiv.org/pdf/2201.05072.pdf | PDF (arXiv)]] |
| * [[https://github.com/CMU-SAFARI/SparseP | Repository (GitHub)]] | * [[https://github.com/CMU-SAFARI/SparseP | Repository (GitHub)]] |
| * Olgun, A., Gómez-Luna, J., Kanellopoulos, K., Salami, B., Hassan, H., Ergin, O., and Mutlu, O. PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM. ACM TACO, 2022. | * Olgun, A., Gómez-Luna, J., Kanellopoulos, K., Salami, B., Hassan, H., Ergin, O., and Mutlu, O., "//PiDRAM: A Holistic End-to-End FPGA-Based Framework for Processing-in-DRAM//." ACM TACO, 2022. |
| * [[https://arxiv.org/pdf/2111.00082.pdf | PDF (arXiv)]] | * [[https://arxiv.org/pdf/2111.00082.pdf | PDF (arXiv)]] |
| * [[https://github.com/cmu-safari/pidram | Repository (GitHub)]] | * [[https://github.com/cmu-safari/pidram | Repository (GitHub)]] |
| * Oliveira, G. F., Gómez-Luna, J., Orosa, L., Ghose, S., Vijaykumar, N., Fernandez, I., Sadrosadati, M., Mutlu, O. DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks. IEEE Access, 2021. | * Oliveira, G. F., Gómez-Luna, J., Orosa, L., Ghose, S., Vijaykumar, N., Fernandez, I., Sadrosadati, M., Mutlu, O., "//DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks//." IEEE Access, 2021. |
| * [[https://arxiv.org/pdf/2105.03725.pdf | PDF (arXiv)]] | * [[https://arxiv.org/pdf/2105.03725.pdf | PDF (arXiv)]] |
| * [[https://github.com/CMU-SAFARI/DAMOV | Repository (GitHub)]] | * [[https://github.com/CMU-SAFARI/DAMOV | Repository (GitHub)]] |
| * Luo, H., Tu, Y. C., Bostancı, F. N., Olgun, A., Ya, A. G., Mutlu, O. Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator. IEEE CAL, 2023. | * Luo, H., Tu, Y. C., Bostancı, F. N., Olgun, A., Ya, A. G., Mutlu, O., "//Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator//." IEEE CAL, 2023. |
| * [[https://arxiv.org/pdf/2308.11030.pdf | PDF (arXiv)]] | * [[https://arxiv.org/pdf/2308.11030.pdf | PDF (arXiv)]] |
| * [[https://github.com/CMU-SAFARI/ramulator2 | Repository (GitHub)]] | * [[https://github.com/CMU-SAFARI/ramulator2 | Repository (GitHub)]] |
| * Olgun, A., Hassan, H., Yağlıkçı, A. G., Tuğrul, Y. C., Orosa, L., Luo, H., Patel, M., Ergin, O., Mutlu, O. DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. IEEE CAD, 2023. | * Olgun, A., Hassan, H., Yağlıkçı, A. G., Tuğrul, Y. C., Orosa, L., Luo, H., Patel, M., Ergin, O., Mutlu, O., "//DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips//." IEEE CAD, 2023. |
| * [[https://arxiv.org/pdf/2211.05838.pdf | PDF (arXiv)]] | * [[https://arxiv.org/pdf/2211.05838.pdf | PDF (arXiv)]] |
| * [[https://github.com/CMU-SAFARI/DRAM-Bender | Repository (GitHub)]] | * [[https://github.com/CMU-SAFARI/DRAM-Bender | Repository (GitHub)]] |
| * Oliveira, G. F., Olgun, A., Yaglikci, A. G., Bostanci, N., Gomez-Luna, J., Ghose, S., Mutlu, O., MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing, in HPCA, 2024. | * Oliveira, G. F., Olgun, A., Yaglikci, A. G., Bostanci, N., Gomez-Luna, J., Ghose, S., Mutlu, O., "//MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing,//" in HPCA, 2024. |
| * [[https://arxiv.org/pdf/2402.19080.pdf | PDF (arXiv)]] | * [[https://arxiv.org/pdf/2402.19080.pdf | PDF (arXiv)]] |
| * [[https://github.com/CMU-SAFARI/MIMDRAM | Repository (GitHub)]] | * [[https://github.com/CMU-SAFARI/MIMDRAM | Repository (GitHub)]] |
| * Hajinazar, N., Oliveira, G. F., Gregorio, S., Ferreira, J. D., Ghiasi, N. M., Patel, M., Alser, M., Ghose, S., Gomez-Luna, J., Mutlu. O., SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM, in ASPLOS, 2021. | * Hajinazar, N., Oliveira, G. F., Gregorio, S., Ferreira, J. D., Ghiasi, N. M., Patel, M., Alser, M., Ghose, S., Gomez-Luna, J., Mutlu. O., "//SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM//," in ASPLOS, 2021. |
| * [[https://arxiv.org/pdf/2105.12839.pdf | PDF (arXiv)]] | * [[https://arxiv.org/pdf/2105.12839.pdf | PDF (arXiv)]] |
| * [[https://www.youtube.com/watch?v=lu3Br4-kySw | Full Talk Video]] | * [[https://www.youtube.com/watch?v=lu3Br4-kySw | Full Talk Video]] |
| * Seshadri, V., Lee, D., Mullins, T., Hassan, H., Boroumand, A., Kim, J., Kozuch, M. A., Mutlu, O., Gibbons, P. B., Mowry, T. C., Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, in MICRO, 2017. | * Seshadri, V., Lee, D., Mullins, T., Hassan, H., Boroumand, A., Kim, J., Kozuch, M. A., Mutlu, O., Gibbons, P. B., Mowry, T. C., "//Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology//," in MICRO, 2017. |
| * [[https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17.pdf | PDF]] | * [[https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17.pdf | PDF]] |
| | * Schwedock, B.C., Yoovidhya, P., Seibert, J. and Beckmann, N., "//Täkō: A Polymorphic Cache Hierarchy for General-Purpose Optimization of Data Movement//," in ISCA, 2022. |
| | * [[https://events.safari.ethz.ch/micro24-memorycentric-tutorial/lib/exe/fetch.php?media=2022.isca.tako.pdf | PDF]] |
| | * Schwedock, B.C. and Beckmann, N., "//Leviathan: A Unified System for General-Purpose Near-Data Computing//," in MICRO, 2024. |
| | * [[https://events.safari.ethz.ch/micro24-memorycentric-tutorial/lib/exe/fetch.php?media=2024.micro.leviathan.pdf | PDF]] |
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