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--- start [2025/06/07 23:20] – [Agenda & Workshop Materials] geraldod
+++ start [2025/06/08 15:38] (current) – [Agenda & Workshop Materials (Tentative)] kkoliogeorgi
@@ Line 46: / Line 46: @@
 | 10:00 AM | Dr. Geraldo F. Oliveira | Processing-Using-Memory (PUM) Systems - Part I   | {{geraldo-ics25-lecture2-PUM-part-I-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture2-PUM-part-I-beforelecture.pptx|(PPT)}} |
 | 10:30 AM | N/A | **Coffee Break** | |
-| 10:45 AM | Ismail E. Yuksel | Functionally-Complete Boolean Logic in Real DRAM Chips  |  |
+| 10:45 AM | Ismail E. Yuksel | Functionally-Complete Boolean Logic in Real DRAM Chips  | {{ics25_mccsys_fcdram_ismail_talk.pdf|(PDF)}} {{ics25_mccsys_fcdram_ismail_talk.pptx|(PPT)}}  |
-| 11:15 AM | Dr. Geraldo F. Oliveira | Processing-Using-Memory (PUM) Systems - Part II |  |
+| 11:15 AM | Dr. Geraldo F. Oliveira | Processing-Using-Memory (PUM) Systems - Part II | {{geraldo-ics25-lecture3-PUM-part-II-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture3-PUM-part-II-beforelecture.pptx|(PPT)}} |
-| 11:45 AM | Dr. Geraldo F. Oliveira | Processing-Near-Memory (PNM) Systems: Academia & Industry Developments - Part I |  |
+| 11:45 AM | Dr. Geraldo F. Oliveira | Processing-Near-Memory (PNM) Systems: Academia & Industry Developments - Part I | {{geraldo-ics25-lecture4-PNM-part-I-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture4-PNM-part-I-beforelecture.pptx|(PPT)}} |
 | 12:00 PM | N/A | **Lunch** | |
-| 01:00 PM | Dr. Geraldo F. Oliveira |Processing-Near-Memory (PNM) Systems: Academia & Industry Developments - Part II  |  |
+| 01:00 PM | Dr. Geraldo F. Oliveira |Processing-Near-Memory (PNM) Systems: Academia & Industry Developments - Part II  | {{geraldo-ics25-lecture5-PNM-part-II-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture5-PNM-part-II-beforelecture.pptx|(PPT)}} |
-| 01:30 PM | Dr. Konstantina Koliogeorgi | PIM Architectures for Bioinformatics  |  |
+| 01:30 PM | Dr. Konstantina Koliogeorgi | PIM Architectures for Bioinformatics  | {{konstantina-ics25-pim-arch-for-genomics.pdf|(PDF)}} {{konstantina-ics25-pim-arch-for-genomics.pptx|(PPT)}} |
-| 02:00 PM | Dr. Geraldo F. Oliveira | PIM Adoption & Programmability |  |
+| 02:00 PM | Dr. Geraldo F. Oliveira | PIM Adoption & Programmability | {{geraldo-ics25-lecture6-adoption-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture6-adoption-beforelecture.pptx|(PPT)}} |
-| 02:30 PM | Dr. Geraldo F. Oliveira | //Proteus//: Achieving High-Performance Processing-Using-DRAM with Dynamic Bit-Precision, Adaptive Data Representation, and Flexible Arithmetic |  |
+| 02:30 PM | Dr. Geraldo F. Oliveira | //Proteus//: Achieving High-Performance Processing-Using-DRAM with Dynamic Bit-Precision, Adaptive Data Representation, and Flexible Arithmetic | {{geraldo_proteus_v1.pdf|(PDF)}} {{geraldo_proteus_v1.pptx|(PPT)}} |
 | 03:00 PM | N/A | **Coffee Break** | |
 | 03:15 PM | Taewoon Kang | SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications |  |
-| 03:45 PM | Prof. Elaheh Sadredini | TBD |  |
+| 03:45 PM | Prof. Elaheh Sadredini | Keep it Close, Keep it Secure! Towards Efficient, Secure, and Programmable Memory-Centric Computing |  |
 | 04:15 PM | Melina Soysal | MARS: Processing-In-Memory Acceleration of Raw Signal Genome Analysis Inside the Storage Subsystem |  |
 | 04:45 PM | Dr. Geraldo F. Oliveira | Closing Remarks |  |
@@ Line 63: / Line 63: @@
 ==== Invited Speakers ====
-TBA
+=== Ismail E. Yüksel (ETH Zurich) ===
+**Talk Title:** Functionally-Complete Boolean Logic in Real DRAM Chip {{ ::ismail_headshot.jpeg?nolink&200|}}
+**Talk Abstract:** We experimentally demonstrate that COTS DRAM chips are capable of performing 1) functionally-complete Boolean operations: NOT, NAND, and NOR and 2) many-input (i.e., more than two-input) AND and OR operations. We present an extensive characterization of new bulk bitwise operations in 256 off-the-shelf modern DDR4 DRAM chips. We evaluate the reliability of these operations using a metric called success rate: the fraction of correctly performed bitwise operations. Among our 19 new observations, we highlight four major results. First, we can perform the NOT operation on COTS DRAM chips with a 98.37% success rate on average. Second, we can perform up to 16-input NAND, NOR, AND, and OR operations on COTS DRAM chips with high reliability (e.g., 16-input NAND, NOR, AND, and OR with an average success rate of 94.94%, 95.87%, 94.94%, and 95.85%, respectively). Third, data pattern only slightly affects bitwise operations. Our results show that executing NAND, NOR, AND, and OR operations with random data patterns decreases the success rate compared to all logic-1/logic-0 patterns by 1.39%, 1.97%, 1.43%, and 1.98%, respectively. Fourth, bitwise operations are highly resilient to temperature changes, with small success rate fluctuations of at most 1.66% when the temperature is increased from 50C to 95C.
+**Bio:** [[https://www.linkedin.com/in/ismail-emir-yuksel |Ismail E. Yüksel]] is a 2nd-year PhD student in the SAFARI Research Group at ETH Zurich under the supervision of Prof.Onur Mutlu. His current broader research interests are in computer architecture, processing-in-memory, and hardware security, focusing on understanding, enhancing, and exploiting fundamental computational capabilities of modern DRAM architectures.
+=== Konstantina Koliogeorgi (ETH Zurich) ===
+**Talk Title:** PIM Architectures for Bioinformatics {{ ::konstantina_headshot.jpeg?nolink&200|}}
+**Talk Abstract:** As bioinformatics workflows grow increasingly data-intensive — from genome sequencing to proteomics and large-scale biological simulations — traditional compute architectures face significant memory bottlenecks. This talk explores the potential of Processing-in-Memory (PIM) architectures to revolutionize bioinformatics by bringing computation closer to the data. We will cover key PIM design principles, highlight recent advancements in PIM-enabled bioinformatics applications (such as sequence alignment), and discuss practical considerations for integrating PIM into existing HPC.
+**Bio:** [[https://www.linkedin.com/in/konstantina-koliogeorgi-256965269 | Konstantina Koliogeorgi]] received the Diploma and Ph.D. degree in Electrical and Computer Engineering from the Microprocessors and Digital Systems Laboratory of the National Technical University of Athens, Greece in 2016 and 2023, respectively.She is currently a Postdoctoral Researcher at ETH Zurich at SAFARI Research Group. Her research activity lies in the field of computer systems, hardware-software co-design, heterogeneous computing and hardware acceleration. She is particularly interested in leveraging these principles for the computational and architectural optimization of genome analysis applications.
+=== Prof. Elaheh Sadredini (University of California, Riverside) ===
+**Talk Title:** Keep it Close, Keep it Secure! Towards Efficient, Secure, and Programmable Memory-Centric Computing {{ ::elaheh_headshot.jpeg?nolink&200|}}
+**Talk Abstract:** Processing-in-memory (PIM) architectures are increasingly promising for accelerating data-intensive workloads, but key challenges remain in making them secure, programmable, and deployable across platforms. This talk presents our efforts to tackle these challenges through the co-design of hardware, software, and security mechanisms that make PIM systems more practical and trustworthy. We develop near-cache and in-SRAM PIM architectures that support a wide range of cryptographic kernels with high internal bandwidth and system integration. To address programmability, we develop a compiler framework that automatically maps high-level code to efficient PIM execution through advanced source transformations, PIM-aware loop optimizations, and cost-driven layout and instruction selection. To enable secure execution, we leverage secure multi-party computation (MPC) as a lightweight, privacy-preserving mechanism that enables secure computing on real-world PIM hardware. Together, these contributions bring PIM systems closer to practical deployment in both cloud and edge environments.
+**Bio:** [[https://www.cs.ucr.edu/~elaheh/ | Elaheh Sadredini]] is an Assistant Professor of Computer Science and Engineering at the University of California, Riverside. Her research broadly focuses on developing secure, high-performance, and energy-efficient data-centric architectures. She received her Ph.D. from the University of Virginia in 2019 and joined UCR in 2020. Her work has appeared in top-tier venues including MICRO, ISCA, ASPLOS, and HPCA, USENIX Security, DAC, ICS, and KDD, and has earned several recognitions, including the NSF CAREER Award, a Best Paper Award at ACM Computing Frontiers, the “Best of CAL” award, and multiple best paper nominations, including HPCA’20, FCCM’20, and IISWC’19. She is also a recipient of the Hellman Fellowship and the John A. Stankovic Graduate Research Award.
+=== Taewoon Kang (Korea University) ===
+**Talk Title:** SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications {{ ::taewoon_headshot.jpg?nolink&200|}}
+**Talk Abstract:** Sparse matrix-vector multiplication (SpMV) is a fundamental operation across diverse domains, including scientific computing, machine learning, and graph processing. However, its irregular memory access patterns necessitate frequent data retrieval from external memory, leading to significant inefficiencies on conventional processors such as CPUs and GPUs. Processing-in-memory (PIM) presents a promising solution to address these performance bottlenecks observed in memory-intensive workloads. However, existing PIM architectures are primarily optimized for dense matrix operations since conventional memory cell structures struggle with the challenges of indirect indexing and unbalanced data distributions inherent in sparse computations.
+In order to address these challenges, we propose SparsePIM, a novel PIM architecture designed to accelerate SpMV computations efficiently. SparsePIM introduces a DRAM row-aligned format (DRAF) to optimize memory access patterns. SparsePIM exploits K-means-based column group partitioning to achieve a balanced load distribution across memory banks. Furthermore, SparsePIM includes bank group (BG) accumulators to mitigate the performance burdens of accumulating partial sums in SpMV operations. By aggregating partial results across multiple banks, SparsePIM can significantly improve the throughput of sparse matrix computations. Leveraging a combination of hardware and software optimizations, SparsePIM can achieve significant performance gains over cuSPARSE-based SpMV kernels on the GPU. Our evaluation demonstrates that SparsePIM achieves up to 5.61x speedup over SpMV on GPUs.
+**Bio:** [[https://csarch.korea.ac.kr/authors/taewoon-kang/ | Taewoon Kang]] is a graduate student pursuing a Ph.D degree (Ph.D./Masters integrated course) in Department of Computer Science and Engineering at Korea University. His research interest lies in near data processing (NDP) and FPGA-based accelerator design. His current research focuses on processing-in-memory (PIM). Taewoon earned his B.S. in System Semiconductor Engineering from Sangmyung University, South Korea.
 === Recommended Materials ===