ICS 2025 Memory Centric Workshop

Processing-in-Memory (PIM) is a computing paradigm that aims to overcome data movement bottlenecks by making memory systems compute-capable. Explored over several decades since the 1960s, PIM systems are now becoming a reality with the advent of the first commercial products and prototypes. PIM can improve performance and energy efficiency for many modern applications. However, there are many open questions spanning the entire computing stack and many challenges for widespread adoption.

This combined tutorial and workshop will focus on the latest advances in PIM technology, spanning both hardware and software. It will include novel PIM ideas, different tools and frameworks for conducting PIM research, and programming techniques and optimization strategies for PIM kernels. First, we will provide a series of lectures and invited talks that will provide an introduction to PIM, including an overview and a rigorous analysis of existing PIM hardware from industry and academia. Second, we will invite the broad PIM research community to submit and present their ongoing work on memory-centric systems. The program committee will favor papers that bring new insights on memory-centric systems or novel PIM-friendly applications, address key system integration challenges in academic or industry PIM architectures, or put forward controversial points of view on the memory-centric execution paradigm. We also consider position papers, especially from industry, that outline design and process challenges affecting PIM systems, new PIM architectures, or system solutions for real state-of-the-art PIM devices.

Time & Location: Sunday 08th, from 09:00 AM (MDT) to 05:00 PM (MDT) at WEB 1230.

This workshop consists of invited talks on the general topic of memory-centric computing systems. There are a limited number of slots for invited talks. If you would like to deliver a talk on related topics, please contact us by filling out this form. The submission deadline is May 16, 2025, 23:59 AoE. We invite abstract submissions related to (but not limited to) the following topics in the context of memory-centric computing systems:

• Design of novel and new processing-in-memory (PIM) architectures, including system solutions for real state-of-the-art PIM devices
• Analysis and mapping of novel applications to state-of-the-art PIM systems
• Programming models and code generation support for PIM
• Runtime engines for adaptive code and data scheduling, data mapping, access control for PIM systems
• Memory coherence mechanisms for collaborative host–PIM execution
• Virtual memory support for a unified host and PIM address space
• Data structures and algorithms for PIM systems
• Infrastructures to assess the benefits and feasibility of PIM systems, including benchmarks and simulation infrastructures for PIM prototyping
• Issues related to robustness and security of PIM systems
• Experimental analysis and benchmarking of real PIM systems

YouTube livestream

Talk Title: Functionally-Complete Boolean Logic in Real DRAM Chip

Talk Abstract: We experimentally demonstrate that COTS DRAM chips are capable of performing 1) functionally-complete Boolean operations: NOT, NAND, and NOR and 2) many-input (i.e., more than two-input) AND and OR operations. We present an extensive characterization of new bulk bitwise operations in 256 off-the-shelf modern DDR4 DRAM chips. We evaluate the reliability of these operations using a metric called success rate: the fraction of correctly performed bitwise operations. Among our 19 new observations, we highlight four major results. First, we can perform the NOT operation on COTS DRAM chips with a 98.37% success rate on average. Second, we can perform up to 16-input NAND, NOR, AND, and OR operations on COTS DRAM chips with high reliability (e.g., 16-input NAND, NOR, AND, and OR with an average success rate of 94.94%, 95.87%, 94.94%, and 95.85%, respectively). Third, data pattern only slightly affects bitwise operations. Our results show that executing NAND, NOR, AND, and OR operations with random data patterns decreases the success rate compared to all logic-1/logic-0 patterns by 1.39%, 1.97%, 1.43%, and 1.98%, respectively. Fourth, bitwise operations are highly resilient to temperature changes, with small success rate fluctuations of at most 1.66% when the temperature is increased from 50C to 95C.

Bio: Ismail E. Yüksel is a 2nd-year PhD student in the SAFARI Research Group at ETH Zurich under the supervision of Prof.Onur Mutlu. His current broader research interests are in computer architecture, processing-in-memory, and hardware security, focusing on understanding, enhancing, and exploiting fundamental computational capabilities of modern DRAM architectures.

Talk Title: PIM Architectures for Bioinformatics

Talk Abstract: As bioinformatics workflows grow increasingly data-intensive — from genome sequencing to proteomics and large-scale biological simulations — traditional compute architectures face significant memory bottlenecks. This talk explores the potential of Processing-in-Memory (PIM) architectures to revolutionize bioinformatics by bringing computation closer to the data. We will cover key PIM design principles, highlight recent advancements in PIM-enabled bioinformatics applications (such as sequence alignment), and discuss practical considerations for integrating PIM into existing HPC.

Bio: Konstantina Koliogeorgi received the Diploma and Ph.D. degree in Electrical and Computer Engineering from the Microprocessors and Digital Systems Laboratory of the National Technical University of Athens, Greece in 2016 and 2023, respectively.She is currently a Postdoctoral Researcher at ETH Zurich at SAFARI Research Group. Her research activity lies in the field of computer systems, hardware-software co-design, heterogeneous computing and hardware acceleration. She is particularly interested in leveraging these principles for the computational and architectural optimization of genome analysis applications.

Talk Title: Keep it Close, Keep it Secure! Towards Efficient, Secure, and Programmable Memory-Centric Computing

Talk Abstract: Processing-in-memory (PIM) architectures are increasingly promising for accelerating data-intensive workloads, but key challenges remain in making them secure, programmable, and deployable across platforms. This talk presents our efforts to tackle these challenges through the co-design of hardware, software, and security mechanisms that make PIM systems more practical and trustworthy. We develop near-cache and in-SRAM PIM architectures that support a wide range of cryptographic kernels with high internal bandwidth and system integration. To address programmability, we develop a compiler framework that automatically maps high-level code to efficient PIM execution through advanced source transformations, PIM-aware loop optimizations, and cost-driven layout and instruction selection. To enable secure execution, we leverage secure multi-party computation (MPC) as a lightweight, privacy-preserving mechanism that enables secure computing on real-world PIM hardware. Together, these contributions bring PIM systems closer to practical deployment in both cloud and edge environments.

Bio: Elaheh Sadredini is an Assistant Professor of Computer Science and Engineering at the University of California, Riverside. Her research broadly focuses on developing secure, high-performance, and energy-efficient data-centric architectures. She received her Ph.D. from the University of Virginia in 2019 and joined UCR in 2020. Her work has appeared in top-tier venues including MICRO, ISCA, ASPLOS, and HPCA, USENIX Security, DAC, ICS, and KDD, and has earned several recognitions, including the NSF CAREER Award, a Best Paper Award at ACM Computing Frontiers, the “Best of CAL” award, and multiple best paper nominations, including HPCA’20, FCCM’20, and IISWC’19. She is also a recipient of the Hellman Fellowship and the John A. Stankovic Graduate Research Award.

Talk Title: SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications

Talk Abstract: Sparse matrix-vector multiplication (SpMV) is a fundamental operation across diverse domains, including scientific computing, machine learning, and graph processing. However, its irregular memory access patterns necessitate frequent data retrieval from external memory, leading to significant inefficiencies on conventional processors such as CPUs and GPUs. Processing-in-memory (PIM) presents a promising solution to address these performance bottlenecks observed in memory-intensive workloads. However, existing PIM architectures are primarily optimized for dense matrix operations since conventional memory cell structures struggle with the challenges of indirect indexing and unbalanced data distributions inherent in sparse computations. In order to address these challenges, we propose SparsePIM, a novel PIM architecture designed to accelerate SpMV computations efficiently. SparsePIM introduces a DRAM row-aligned format (DRAF) to optimize memory access patterns. SparsePIM exploits K-means-based column group partitioning to achieve a balanced load distribution across memory banks. Furthermore, SparsePIM includes bank group (BG) accumulators to mitigate the performance burdens of accumulating partial sums in SpMV operations. By aggregating partial results across multiple banks, SparsePIM can significantly improve the throughput of sparse matrix computations. Leveraging a combination of hardware and software optimizations, SparsePIM can achieve significant performance gains over cuSPARSE-based SpMV kernels on the GPU. Our evaluation demonstrates that SparsePIM achieves up to 5.61x speedup over SpMV on GPUs.

Bio: Taewoon Kang is a graduate student pursuing a Ph.D degree (Ph.D./Masters integrated course) in Department of Computer Science and Engineering at Korea University. His research interest lies in near data processing (NDP) and FPGA-based accelerator design. His current research focuses on processing-in-memory (PIM). Taewoon earned his B.S. in System Semiconductor Engineering from Sangmyung University, South Korea.

• Mutlu, O., Ghose, S., Gómez-Luna, J., and Ausavarungnirun, R., “A Modern Primer on Processing in Memory.” In Emerging Computing: From Devices to Systems, 2023.
  • PDF (arXiv)
• Gómez-Luna, J., El Hajj, I., Fernandez, I., Giannoula, C., Oliveira, G. F., and Mutlu, O., “Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System.” IEEE Access, 2022.
  • PDF (arXiv)
  • Repository (GitHub)
• Giannoula, C., Fernandez, I., Gómez-Luna, J., Koziris, N., Goumas, G., and Mutlu, O., “SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures,” in SIGMETRICS 2022.
  • PDF (arXiv)
  • Repository (GitHub)
• Olgun, A., Gómez-Luna, J., Kanellopoulos, K., Salami, B., Hassan, H., Ergin, O., and Mutlu, O., “PiDRAM: A Holistic End-to-End FPGA-Based Framework for Processing-in-DRAM.” ACM TACO, 2022.
  • PDF (arXiv)
  • Repository (GitHub)
• Oliveira, G. F., Gómez-Luna, J., Orosa, L., Ghose, S., Vijaykumar, N., Fernandez, I., Sadrosadati, M., Mutlu, O., “DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks.” IEEE Access, 2021.
  • PDF (arXiv)
  • Repository (GitHub)
• Luo, H., Tu, Y. C., Bostancı, F. N., Olgun, A., Ya, A. G., Mutlu, O., “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator.” IEEE CAL, 2023.
  • PDF (arXiv)
  • Repository (GitHub)
• Olgun, A., Hassan, H., Yağlıkçı, A. G., Tuğrul, Y. C., Orosa, L., Luo, H., Patel, M., Ergin, O., Mutlu, O., “DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips.” IEEE CAD, 2023.
  • PDF (arXiv)
  • Repository (GitHub)
• Oliveira, G. F., Olgun, A., Yaglikci, A. G., Bostanci, N., Gomez-Luna, J., Ghose, S., Mutlu, O., “MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing,” in HPCA, 2024.
  • PDF (arXiv)
  • Repository (GitHub)
• Hajinazar, N., Oliveira, G. F., Gregorio, S., Ferreira, J. D., Ghiasi, N. M., Patel, M., Alser, M., Ghose, S., Gomez-Luna, J., Mutlu. O., “SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM,” in ASPLOS, 2021.
  • PDF (arXiv)
  • Full Talk Video
• Seshadri, V., Lee, D., Mullins, T., Hassan, H., Boroumand, A., Kim, J., Kozuch, M. A., Mutlu, O., Gibbons, P. B., Mowry, T. C., “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” in MICRO, 2017.
  • PDF
• Schwedock, B.C., Yoovidhya, P., Seibert, J. and Beckmann, N., “Täkō: A Polymorphic Cache Hierarchy for General-Purpose Optimization of Data Movement,” in ISCA, 2022.
  • PDF
• Schwedock, B.C. and Beckmann, N., “Leviathan: A Unified System for General-Purpose Near-Data Computing,” in MICRO, 2024.
  • PDF

• Mutlu O., Memory-Centric Computing (IMACAW Keynote Talk at DAC 2023), July 2023:
  • PDF PPT Video
• Processing-in-Memory: A Workload-Driven Perspective (summary paper about recent research in PIM):
  • PDF
• Processing Data Where It Makes Sense: Enabling In-Memory Computation (summary paper about recent research in PIM):
  • PDF
• Processing-in-Memory course (Spring 2022):
  • Course website
• Gómez-Luna, J., and Mutlu, O., Data-Centric Architectures: Fundamentally Improving Performance and Energy (227-0085-37L), ETH Zürich, Fall 2022.
  • Course Website
  • Lecture Playlist
  • PDF (arXiv)