ICS 2025 Memory Centric Workshop

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start [2025/06/08 00:35] – geraldodstart [2025/06/08 15:38] (current) – [Agenda & Workshop Materials (Tentative)] kkoliogeorgi
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 | 10:00 AM | Dr. Geraldo F. Oliveira | Processing-Using-Memory (PUM) Systems - Part I   | {{geraldo-ics25-lecture2-PUM-part-I-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture2-PUM-part-I-beforelecture.pptx|(PPT)}} | | 10:00 AM | Dr. Geraldo F. Oliveira | Processing-Using-Memory (PUM) Systems - Part I   | {{geraldo-ics25-lecture2-PUM-part-I-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture2-PUM-part-I-beforelecture.pptx|(PPT)}} |
 | 10:30 AM | N/A | **Coffee Break** | | | 10:30 AM | N/A | **Coffee Break** | |
-| 10:45 AM | Ismail E. Yuksel | Functionally-Complete Boolean Logic in Real DRAM Chips  |  |+| 10:45 AM | Ismail E. Yuksel | Functionally-Complete Boolean Logic in Real DRAM Chips  | {{ics25_mccsys_fcdram_ismail_talk.pdf|(PDF)}} {{ics25_mccsys_fcdram_ismail_talk.pptx|(PPT)}}  |
 | 11:15 AM | Dr. Geraldo F. Oliveira | Processing-Using-Memory (PUM) Systems - Part II | {{geraldo-ics25-lecture3-PUM-part-II-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture3-PUM-part-II-beforelecture.pptx|(PPT)}} | | 11:15 AM | Dr. Geraldo F. Oliveira | Processing-Using-Memory (PUM) Systems - Part II | {{geraldo-ics25-lecture3-PUM-part-II-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture3-PUM-part-II-beforelecture.pptx|(PPT)}} |
 | 11:45 AM | Dr. Geraldo F. Oliveira | Processing-Near-Memory (PNM) Systems: Academia & Industry Developments - Part I | {{geraldo-ics25-lecture4-PNM-part-I-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture4-PNM-part-I-beforelecture.pptx|(PPT)}} | | 11:45 AM | Dr. Geraldo F. Oliveira | Processing-Near-Memory (PNM) Systems: Academia & Industry Developments - Part I | {{geraldo-ics25-lecture4-PNM-part-I-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture4-PNM-part-I-beforelecture.pptx|(PPT)}} |
 | 12:00 PM | N/A | **Lunch** | | | 12:00 PM | N/A | **Lunch** | |
 | 01:00 PM | Dr. Geraldo F. Oliveira |Processing-Near-Memory (PNM) Systems: Academia & Industry Developments - Part II  | {{geraldo-ics25-lecture5-PNM-part-II-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture5-PNM-part-II-beforelecture.pptx|(PPT)}} | | 01:00 PM | Dr. Geraldo F. Oliveira |Processing-Near-Memory (PNM) Systems: Academia & Industry Developments - Part II  | {{geraldo-ics25-lecture5-PNM-part-II-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture5-PNM-part-II-beforelecture.pptx|(PPT)}} |
-| 01:30 PM | Dr. Konstantina Koliogeorgi | PIM Architectures for Bioinformatics  |  |+| 01:30 PM | Dr. Konstantina Koliogeorgi | PIM Architectures for Bioinformatics  | {{konstantina-ics25-pim-arch-for-genomics.pdf|(PDF)}} {{konstantina-ics25-pim-arch-for-genomics.pptx|(PPT)}} |
 | 02:00 PM | Dr. Geraldo F. Oliveira | PIM Adoption & Programmability | {{geraldo-ics25-lecture6-adoption-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture6-adoption-beforelecture.pptx|(PPT)}} | | 02:00 PM | Dr. Geraldo F. Oliveira | PIM Adoption & Programmability | {{geraldo-ics25-lecture6-adoption-beforelecture.pdf|(PDF)}} {{geraldo-ics25-lecture6-adoption-beforelecture.pptx|(PPT)}} |
-| 02:30 PM | Dr. Geraldo F. Oliveira | //Proteus//: Achieving High-Performance Processing-Using-DRAM with Dynamic Bit-Precision, Adaptive Data Representation, and Flexible Arithmetic |  |+| 02:30 PM | Dr. Geraldo F. Oliveira | //Proteus//: Achieving High-Performance Processing-Using-DRAM with Dynamic Bit-Precision, Adaptive Data Representation, and Flexible Arithmetic | {{geraldo_proteus_v1.pdf|(PDF)}} {{geraldo_proteus_v1.pptx|(PPT)}} |
 | 03:00 PM | N/A | **Coffee Break** | | | 03:00 PM | N/A | **Coffee Break** | |
 | 03:15 PM | Taewoon Kang | SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications |  | | 03:15 PM | Taewoon Kang | SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications |  |
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 ==== Invited Speakers ==== ==== Invited Speakers ====
  
-=== Ismail E. Yüksek (ETH Zurich) ===  +=== Ismail E. Yüksel (ETH Zurich) ===  
 **Talk Title:** Functionally-Complete Boolean Logic in Real DRAM Chip {{ ::ismail_headshot.jpeg?nolink&200|}} **Talk Title:** Functionally-Complete Boolean Logic in Real DRAM Chip {{ ::ismail_headshot.jpeg?nolink&200|}}
  
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-**Bio:** [[https://www.linkedin.com/in/ismail-emir-yuksel |Ismail E. Yüksek]] is a 2nd-year PhD student in the SAFARI Research Group at ETH Zurich under the supervision of Prof.Onur Mutlu. His current broader research interests are in computer architecture, processing-in-memory, and hardware security, focusing on understanding, enhancing, and exploiting fundamental computational capabilities of modern DRAM architectures.+**Bio:** [[https://www.linkedin.com/in/ismail-emir-yuksel |Ismail E. Yüksel]] is a 2nd-year PhD student in the SAFARI Research Group at ETH Zurich under the supervision of Prof.Onur Mutlu. His current broader research interests are in computer architecture, processing-in-memory, and hardware security, focusing on understanding, enhancing, and exploiting fundamental computational capabilities of modern DRAM architectures.
  
 === Konstantina Koliogeorgi (ETH Zurich) ===   === Konstantina Koliogeorgi (ETH Zurich) ===  
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 === Prof. Elaheh Sadredini (University of California, Riverside) ===   === Prof. Elaheh Sadredini (University of California, Riverside) ===  
-**Talk Title:** Keep it Close, Keep it Secure! Towards Efficient, Secure, and Programmable Memory-Centric Computing {{::elaheh_headshot.jpeg?nolink&200|}}+**Talk Title:** Keep it Close, Keep it Secure! Towards Efficient, Secure, and Programmable Memory-Centric Computing {{ ::elaheh_headshot.jpeg?nolink&200|}} 
  
 **Talk Abstract:** Processing-in-memory (PIM) architectures are increasingly promising for accelerating data-intensive workloads, but key challenges remain in making them secure, programmable, and deployable across platforms. This talk presents our efforts to tackle these challenges through the co-design of hardware, software, and security mechanisms that make PIM systems more practical and trustworthy. We develop near-cache and in-SRAM PIM architectures that support a wide range of cryptographic kernels with high internal bandwidth and system integration. To address programmability, we develop a compiler framework that automatically maps high-level code to efficient PIM execution through advanced source transformations, PIM-aware loop optimizations, and cost-driven layout and instruction selection. To enable secure execution, we leverage secure multi-party computation (MPC) as a lightweight, privacy-preserving mechanism that enables secure computing on real-world PIM hardware. Together, these contributions bring PIM systems closer to practical deployment in both cloud and edge environments.  **Talk Abstract:** Processing-in-memory (PIM) architectures are increasingly promising for accelerating data-intensive workloads, but key challenges remain in making them secure, programmable, and deployable across platforms. This talk presents our efforts to tackle these challenges through the co-design of hardware, software, and security mechanisms that make PIM systems more practical and trustworthy. We develop near-cache and in-SRAM PIM architectures that support a wide range of cryptographic kernels with high internal bandwidth and system integration. To address programmability, we develop a compiler framework that automatically maps high-level code to efficient PIM execution through advanced source transformations, PIM-aware loop optimizations, and cost-driven layout and instruction selection. To enable secure execution, we leverage secure multi-party computation (MPC) as a lightweight, privacy-preserving mechanism that enables secure computing on real-world PIM hardware. Together, these contributions bring PIM systems closer to practical deployment in both cloud and edge environments. 
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 === Taewoon Kang (Korea University) ===   === Taewoon Kang (Korea University) ===  
-**Talk Title:** SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications {{::taewoon_headshot.jpg?nolink&200|}}+**Talk Title:** SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications {{ ::taewoon_headshot.jpg?nolink&200|}}
  
 **Talk Abstract:** Sparse matrix-vector multiplication (SpMV) is a fundamental operation across diverse domains, including scientific computing, machine learning, and graph processing. However, its irregular memory access patterns necessitate frequent data retrieval from external memory, leading to significant inefficiencies on conventional processors such as CPUs and GPUs. Processing-in-memory (PIM) presents a promising solution to address these performance bottlenecks observed in memory-intensive workloads. However, existing PIM architectures are primarily optimized for dense matrix operations since conventional memory cell structures struggle with the challenges of indirect indexing and unbalanced data distributions inherent in sparse computations. **Talk Abstract:** Sparse matrix-vector multiplication (SpMV) is a fundamental operation across diverse domains, including scientific computing, machine learning, and graph processing. However, its irregular memory access patterns necessitate frequent data retrieval from external memory, leading to significant inefficiencies on conventional processors such as CPUs and GPUs. Processing-in-memory (PIM) presents a promising solution to address these performance bottlenecks observed in memory-intensive workloads. However, existing PIM architectures are primarily optimized for dense matrix operations since conventional memory cell structures struggle with the challenges of indirect indexing and unbalanced data distributions inherent in sparse computations.
start.1749342939.txt.gz · Last modified: 2025/06/08 00:35 by geraldod
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