MCCSys@ICS'26

About

Processing-in-Memory (PIM) is a computing paradigm that aims to overcome data movement bottlenecks by making memory systems compute-capable. Explored over several decades since the 1960s, PIM systems are now becoming a reality with the advent of the first commercial products and prototypes. PIM can improve performance and energy efficiency for many modern applications. However, there are many open questions spanning the entire computing stack and many challenges for widespread adoption.

This combined tutorial and workshop will focus on the latest advances in PIM technology, spanning both hardware and software. It will include novel PIM ideas, different tools and frameworks for conducting PIM research, and programming techniques and optimization strategies for PIM kernels. First, we will provide a series of lectures and invited talks that will provide an introduction to PIM, including an overview and a rigorous analysis of existing PIM hardware from industry and academia. Second, we will invite the broad PIM research community to submit and present their ongoing work on memory-centric systems. The program committee will favor papers that bring new insights on memory-centric systems or novel PIM-friendly applications, address key system integration challenges in academic or industry PIM architectures, or put forward controversial points of view on the memory-centric execution paradigm. We also consider position papers, especially from industry, that outline design and process challenges affecting PIM systems, new PIM architectures, or system solutions for real state-of-the-art PIM devices.

Call for Papers

We invite extended abstract submissions related to (but not limited to) the following topics in the context of memory-centric computing systems:

• Design of novel and new processing-in-memory (PIM) architectures, including system solutions for real state-of-the-art PIM devices
• Analysis and mapping of novel applications to state-of-the-art PIM systems
• Programming models and code generation support for PIM
• Runtime engines for adaptive code and data scheduling, data mapping, access control for PIM systems
• Memory coherence mechanisms for collaborative host–PIM execution
• Virtual memory support for a unified host and PIM address space
• Data structures and algorithms for PIM systems
• Infrastructures to assess the benefits and feasibility of PIM systems, including benchmarks and simulation infrastructures for PIM prototyping
• Issues related to robustness and security of PIM systems
• Experimental analysis and benchmarking of real PIM systems

Please submit your extended abstract by filling out this form.

Key Dates

Agenda & Workshop Materials

July 6th, 2026 (09:00 – 17:35) · Room: TBA

Invited Speakers

Daehyeon Baek

Samsung SDS

"Omni-MP: Practical PIM Matrix Mapping for Accelerating LLM Inference on a Real PIM Hardware"

Short Bio: Daehyeon Baek is a Senior Engineer at Samsung SDS. His recent work focuses on an efficient AI serving platform on the Samsung Cloud Platform, including top-tier conference publications such as ISCA, and HPCA. He holds a B.S., M.S., and Ph.D. in Computer Science from the Korea Advanced Institute of Science and Technology.

Abstract: The rapid growth of large language models (LLMs) has led to heavy demands for data and computation. Processing-in-Memory (PIM) technologies integrate processing units into DRAM chips to maximize memory bandwidth by eliminating off-chip data movement, thereby accelerating memory-intensive operations such as General Matrix-Vector Multiplication (GEMV). However, existing PIM hardware and software stacks provide non-optimized GEMV operations with respect to matrix dimensions, which poses challenges for transformer-based LLM inference where GEMV operations occur across diverse dimensions. To address this limitation, we propose Omni-Matrix PIM mapping (Omni-MP), a flexible PIM-GEMV offloading mechanism evaluated on a pre-commercial prototype HBM2-based PIM accelerator. Omni-MP enhances the performance of all GEMV operations during inference by optimizing diverse weight matrix transformations on both fully-connected and attention layers. With these optimizations, Omni-MP significantly improves end-to-end LLM inference performance for 40.2% on average, over GPU-only inference.

Sunchae Kim

University of Toronto

"SumcheckPIM: An Efficient HBM-Based PIM Architecture for Linear Complexity Zero Knowledge Proofs"

Short Bio: Sunchae Kim is an undergraduate student at University of Toronto engineering science program entering fourth year. His main interests are in security, privacy, and computer architecture.

Abstract: Zero-knowledge proofs (ZKPs) are emerging as a core technology for privacy-preserving computation. Despite steady progress in protocol and algorithm design, generating these proofs remains computationally intensive, driving growing interest in hardware acceleration for kernels such as number-theoretic transform (NTT) and multi-scalar multiplication (MSM). Among them, the sumcheck protocol offers a compelling alternative with 𝑂(𝑛) prover complexity compared to 𝑂(𝑛 log 𝑛) for NTT-based approaches, yet our analysis reveals its execution is fundamentally memory-bound, with severely underutilized compute. This characteristic demands a memory-centric acceleration strategy, in contrast to compute-centric approaches of prior work. To this end, we propose SumcheckPIM, an HBM-based processing-in-memory architecture optimized for the sumcheck protocol. SumcheckPIM introduces 256-bit modular arithmetic units at the bank level to support real-world field sizes, a Fiat-Shamir unit on the logic die for global accumulation and challenge generation, and an inter-bank processing unit enabling protocol completion without host interaction. We also propose a DRAM-aware folding scheme that maximizes row buffer locality through row packing and bank ping-ponging. Our design achieves this while maintaining JEDEC compliance with minimal modifications to existing commercial HBM-PIM architectures. We demonstrate that SumcheckPIM delivers both high performance and efficiency, achieving 5.3×–13.3× and 334.2×–361.1× speedup over GPU and CPU baselines, respectively.

Tatsuya Kubo

University of Tokyo

"MVDRAM: Using Real DRAM to Accelerate Matrix-Vector Multiplication in LLM Inference"

Short Bio: Tatsuya Kubo is a Ph.D. student at The University of Tokyo, advised by Prof. Shinya Takamaeda-Yamazaki. His research interests are in computer architecture and Processing-In-Memory, with a focus on exploiting the computational capabilities of commodity DRAM to accelerate AI and data-intensive workloads.

Abstract: Processing-Using-DRAM (PUD) repurposes existing DRAM circuitry to perform massively parallel bit-wise computation directly on the operands stored in each DRAM column, promising to mitigate the memory-bandwidth bottleneck of data-intensive workloads. However, because every general matrix-vector multiplication (GeMV) in large language model (LLM) inference consumes a new input activation vector produced by the processor, prior PUD designs would entail replicating and writing each vector into every DRAM column, making it difficult to achieve end-to-end speedup over processor-based execution. We present MVDRAM, a PUD method that delivers this end-to-end speedup by encoding the input directly into the PUD operation sequence rather than writing it into the DRAM array. MVDRAM combines two complementary techniques: ANDI-based multiplication eliminates input-vector writing by realizing the multiplication of a weight row by an input bit as a single RowCopy that copies either the weight row or an all-zero row according to the input bit, and bit-plane accumulation (BPA) restores full column parallelism under this row-wide multiplication by laying out the weight matrix as bit planes along DRAM rows. Hardware evaluation on real DDR4 modules with a custom FPGA controller demonstrates 1.33× speedup and 1.70× energy efficiency over a processor-based execution for 8-bit LLM inference.

Livestream

Organizers

Ismail Emir Yuksel

ETH Zürich

Ismail Emir Yuksel is a 3rd-year PhD student in the SAFARI Research Group at ETH Zurich under the supervision of Prof. Onur Mutlu. His current broader research interests are in computer architecture, processing-in-memory, and hardware security, focusing on understanding, enhancing, and exploiting fundamental computational capabilities of modern DRAM architectures. His recent publications show that commodity DRAM chips, without any modification to the chip itself (only with modifications to the memory controller), are able to execute bulk-bitwise computation and data movement operations (including NAND, NOR, NOT, AND, OR, MAJority, multi-row copy, and initialization functions) in a reasonably robust manner.

📧 ismail.yuksel@safari.ethz.ch

F. Nisa Bostanci

ETH Zürich

F. Nisa Bostanci is a fourth-year PhD student in the SAFARI Research Group at ETH Zurich, under the supervision of Prof. Onur Mutlu. She is broadly interested in computer architecture and, more specifically, in security, reliability, and safety (robustness) of memory systems, emerging memory and computation paradigms, including Processing-In-Memory architectures (PIM), and designing effective and efficient solutions to address robustness issues in modern and future systems. Her recent works uncover and mitigate new security vulnerabilities that emerge with the adoption of read disturbance solutions and PIM architectures to aid in designing robust future systems.

📧 nisa.bostanci@safari.ethz.ch

Ataberk Olgun

ETH Zürich

Ataberk Olgun is a senior PhD student at ETH Zurich, working with Prof. Onur Mutlu. His broad research interests include designing secure, high-performance, and energy-efficient DRAM architectures. Especially with the worsening RowHammer vulnerability, it is increasingly difficult to design new DRAM architectures that satisfy all three characteristics. His current research focuses on i) deeply understanding and ii) efficiently mitigating the RowHammer vulnerability in modern systems.

📧 ataberk.olgun@safari.ethz.ch

Professor Onur Mutlu

ETH Zürich

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He previously held the William D. and Nancy W. Strecker Early Career Professorship at Carnegie Mellon University. His research interests are in computer architecture, computing systems, hardware security, memory & storage systems, and bioinformatics, with a major focus on designing fundamentally energy-efficient, high-performance, and robust computing systems. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held product, research and visiting positions at Intel Corporation, Advanced Micro Devices, VMware, Google, and Stanford University. He received various honors for his research, including the 2025 IEEE Computer Society Harry H. Goode Memorial Award “for seminal contributions to computer architecture research and practice, especially in memory systems.” He is an ACM Fellow, IEEE Fellow, and an elected member of the Academy of Europe. He enjoys teaching, mentoring, and enabling & democratizing access to high-quality research and education. He has supervised 25 PhD graduates, many of whom received major dissertation awards, 18 postdoctoral trainees, and more than 70 Master’s and Bachelor’s students. His computer architecture and digital logic design course lectures and materials are freely available on YouTube and his research group makes a wide variety of artifacts freely available online. For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.

📧 onur.mutlu@safari.ethz.ch

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