MCCSys@ISCA'26

About

Processing-in-Memory (PIM) is a computing paradigm that aims to overcome data movement bottlenecks by making memory systems compute-capable. Explored over several decades since the 1960s, PIM systems are now becoming a reality with the advent of the first commercial products and prototypes. PIM can improve performance and energy efficiency for many modern applications. However, there are many open questions spanning the entire computing stack and many challenges for widespread adoption.

This combined tutorial and workshop will focus on the latest advances in PIM technology, spanning both hardware and software. It will include novel PIM ideas, different tools and frameworks for conducting PIM research, and programming techniques and optimization strategies for PIM kernels. First, we will provide a series of lectures and invited talks that will provide an introduction to PIM, including an overview and a rigorous analysis of existing PIM hardware from industry and academia. Second, we will invite the broad PIM research community to submit and present their ongoing work on memory-centric systems. The program committee will favor papers that bring new insights on memory-centric systems or novel PIM-friendly applications, address key system integration challenges in academic or industry PIM architectures, or put forward controversial points of view on the memory-centric execution paradigm. We also consider position papers, especially from industry, that outline design and process challenges affecting PIM systems, new PIM architectures, or system solutions for real state-of-the-art PIM devices.

Agenda & Workshop Materials

June 28th, 2026 (08:30 – 18:10) · Room: 306B

Invited Speakers

Liu Liu

Rensselaer Polytechnic Institute

"Memory-Centric Scaling of LLM Decoding Through Contextual Sparsity"

Short Bio: Liu Liu is an Assistant Professor in the Department of Electrical, Computer, and Systems Engineering and the Department of Computer Science at Rensselaer Polytechnic Institute (RPI). He holds a Ph.D. in Computer Science and an M.S. in Electrical and Computer Engineering from the University of California, Santa Barbara. His research focuses on efficient AI computing systems and architecture design. He is a recipient of NSF CAREER Award (2025), Samsung Global Research Outreach Award (2023), and Peter J Frenkel Fellowship (2020) from the Institute of Energy Efficiency at UCSB.

Abstract: Large language model inference is increasingly limited by the cost of moving contextual data, particularly the key-value cache, through the memory hierarchy. This talk presents a memory-centric view of scaling LLM decoding through contextual sparsity in memory access: not all context must be read at full precision, and not all prior tokens must be accessed individually. It presents two works: BitWeaver [ICS’25], which enables read-time precision scaling by retrieving stored data at dynamically truncated bitwidths, and STARC [ASPLOS’26], which improves sparse token access on PIM systems through clustering and remapping of semantically similar KV tokens. Together, these works suggest that future memory-centric LLM systems should expose sparsity-aware control over what context is read, at what precision, and from which memory layout, improving bandwidth efficiency, energy efficiency, and PIM utilization.

Murali Annavaram

Affiliation

"Efficient Large Language Model Acceleration Using HBM-Based PIM Architectures"

Short Bio: Murali Annavaram has been a faculty member in the Ming-Hsieh Department of Electrical Engineering at the University of Southern California from 2007. He currently holds the Robert G. and Mary G. Lane Early Career Chair. His research focuses on energy efficiency and reliability of computing platforms. On the mobile platform end, his research focuses on energy efficient sensor management for body area sensor networks for continuous and real-time health monitoring. He also has an active research group focused on computer systems architecture exploring reliability challenges in the future CMOS technologies. Murali received NSF CAREER award in 2010 and an IBM Faculty Partnership award in 2009. He is also passionate about his teaching. He received the Stevens Institute's Innovation Inside curriculum award for jointly developing a mobile systems design course. Prior to his appointment at USC, he was a senior research scientist at the Intel Microprocessor Research Labs from 2001 to 2007 working on energy efficient server design and 3D stacking architectures. In 2007 he was a visiting researcher at the Nokia Research Center, Palo Alto working on virtual trip line based traffic sensing. His work on Energy Per Instruction Throttling at Intel is implemented in Intel Core i7 processor to turbo boost performance at a fixed power budget. His work on Virtual-Trip-Lines at Nokia formed the foundation for Nokia Traffic Works product that provides real time traffic sensing using mobile phones. He received the Ph.D. degree in Computer Engineering from the University of Michigan, Ann Arbor, in 2001. He is a Senior Member of IEEE and ACM.

Abstract: Large Language Models (LLMs) increasingly suffer from high memory bandwidth demands and data movement overheads, motivating the need for more efficient memory-centric architectures. In this talk, we present our recent research on HBM-based Processing-in-Memory (PIM) architectures for efficient LLM acceleration. We discuss architectural techniques that leverage in-memory computation and lightweight hardware support to improve execution efficiency while reducing unnecessary data movement. The talk will cover the motivation, architectural design, and optimization strategies for scalable LLM acceleration using modern HBM-based PIM systems.

Peiming Yang

University of Toronto

"DCC: Data-Centric Compilation of Machine Learning Kernels for Processing-In-Memory Architectures "

Short Bio: Peiming Yang is a third-year Ph.D. student in Computer Science at the University of Toronto, advised by Professor Gennady Pekhimenko and Christina Giannoula. His research focuses on systems for deep learning, particularly the design of efficient infrastructures for machine learning training and inference through system-level optimizations and compilation technologies. His recent research focuses on designing an ML compiler for Processing-In-Memory systems.

Abstract: High-performance Host processors can integrate Processing-In-Memory (PIM) devices, which can accelerate memory-intensive kernels of Machine Learning (ML) models, including Large Language Models (LLMs), by leveraging the large memory bandwidth available at PIM cores. However, Host processor needs consecutive elements distributed across DRAM banks, while PIM cores need consecutive elements within their local banks. This necessitates data rearrangements in ML kernel execution that pose significant performance and programmability challenges, further exacerbated by the need to support diverse PIM devices. Current compilation approaches lack systematic optimization for diverse ML kernels and multiple PIM devices, and may largely ignore data rearrangement costs during the compute code optimization step. In our work. we show that data rearrangements and compute code optimization are interdependent, and need to be jointly optimized during the tuning process. Therefore, in this talk, we will introduce DCC, the first data-centric ML compiler for PIM systems that jointly co-optimizes data rearrangements and compute code in a unified tuning process. DCC integrates a multi-layer PIM abstraction to support multiple PIM backends. DCC enables effective co-optimization of data partitioning strategies with compute loop partitioning schemes. DCC applies PIM-specific code optimizations, and leverages a fast and accurate performance prediction model to select the best-performing code schedule for a given kernel on a target PIM architecture. Our evaluations show that DCC provides significant performance benefits across various ML kernels, LLMs, and PIM backends. DCC is open-sourced at https://github.com/SPIN-Research-Group/DCC.

Prashant Nair

University of British Columbia

"Scaling the Memory Wall: Towards 3D-DRAM-based Accelerators for Efficient Generative Inference"

Short Bio: Prashant J. Nair is an Associate Professor at the University of British Columbia (UBC) and also the lead architect of the 3D-memory architecture at d-Matrix. He leads the Systems and Architectures (STAR) Lab at UBC and is also an Affiliate Fellow of the Quantum Algorithms Institute. His research focuses on memory architectures and systems. Dr. Nair’s recognitions include the 2024 TCCA Young Architect Award, the 2025 DSN Test of Time Award, the HPCA 2023 Best Paper Award, a MICRO 2024 Best Paper nomination, and the HPCA 2025 Distinguished Artifact Award. Over the past decade, he has published more than 40 papers in top-tier venues. Prior to his promotion to Associate Professor, as an Assistant Professor, he was inducted into all three halls of fame of computer architecture: ISCA, MICRO, and HPCA.

Abstract: Generative AI now underpins search, digital assistants, and media applications, making inference cost a first-order design constraint. Unlike traditional compute-bound workloads, large language and speech models are typically limited by memory bandwidth and capacity rather than raw arithmetic throughput. Thus, their inference cost is driven as much by data movement as by compute, and therefore hinges on the memory system’s design. This concern is especially acute during autoregressive decoding, which must repeatedly stream model weights and key-value (KV) caches at high bandwidths and low latencies while also providing enough capacity to support long context windows and several concurrent users. To make matters worse, these demands are accelerating with state-of-the-art models now exceeding hundreds of billions of parameters, context windows expanding from 4K to 128K tokens and beyond, and mixture-of-experts designs introducing additional irregularity in memory access patterns. Thus, today’s memory technologies force difficult trade-offs. SRAM can deliver extremely high bandwidth, but at prohibitive area and capacity limits. HBM offers higher capacity, but remains constrained by achievable bandwidth and I/O power. Closing this gap will require a fundamental rethinking of how memory is integrated with accelerator logic. In this talk I will introduce our upcoming ISCA 2026 paper on the upcoming memory-centric accelerator from d-Matrix. This accelerator vertically integrates logic with 3D-stacked DRAM to deliver SRAM-level bandwidth and HBM-class capacity while substantially reducing energy consumption. I will describe the architectural challenges addressed by workload-aware channel mapping, optimized power management, topology-preserving redundancy, and thermal-aware reliability mechanisms, enabling the practical deployment of 3D-DRAM. Evaluations using models such as Llama-3.1, DeepSeek-V3, Canary, and Whisper show that our accelerator achieves significantly higher throughput and interactivity compared to HBM-based alternatives. I will conclude by examining the broader implications for computer architecture, particularly how advanced logic-memory integration through hybrid bonding and multi-high stacking can reshape inference cost structures and enable the next generation of trillion-parameter models.

Yilong Zhao

Shanghai Jiao Tong University

"Efficient Memory Management and Access Mechanisms for CPU-PIM Co-Execution Systems"

Short Bio: Yilong Zhao is a Ph.D. candidate in the School of Computer Science at Shanghai Jiao Tong University (SJTU), where he is advised by Prof. Li Jiang and is a member of the IMPACT Lab. His research focuses on in-memory computing architectures and AI acceleration, with multiple papers published in top-tier conferences such as ISCA and ASPLOS. He received his master's and bachelor's degrees from SJTU in 2021 and 2018, respectively.

Abstract: Processing-in-Memory (PIM) is a promising paradigm to overcome the "memory wall," yet its practical deployment is severely hindered by memory management overheads and hardware resource contention during CPU-PIM co-execution. To address these challenges, this presentation explores efficient memory management and access mechanisms to enable seamless, low-interference CPU-PIM coexistence across multiple system layers. UM-PIM (ISCA '24) is presented as a system-level architecture that establishes a uniform and shared memory space with dual-track management, achieving zero-copy task offloading while preserving the host CPU's interleaving bandwidth. Moving to the application layer, PUSHtap (ASPLOS '25) leverages concurrent CPU-PIM access through a unified data storage format with two-dimensional alignment to resolve the data-format dilemma in HTAP databases. Finally, COSM (ISCA '26) introduces an architectural-level cooperative scheduling framework tailored for mobile devices, mitigating bank conflicts and bus congestion during concurrent LLM inference via idleness-aware command insertion. Together, these multi-level techniques demonstrate that co-designing memory architectures, software interfaces, and scheduling policies can effectively eliminate interference, providing critical insights for building an efficient and harmonious CPU-PIM co-execution ecosystem.

Zhenhua Zhu

Tsinghua Shenzhen International Graduate School

"Simulation, Compilation, and Deployment Optimization for Near-DRAM Processing Architectures"

Short Bio: Zhenhua Zhu is an Assistant Professor at Tsinghua Shenzhen International Graduate School (SIGS) and a Visiting Scholar at HKUST. He received his Ph.D. and B.S. degrees from the Department of Electronic Engineering, Tsinghua University, in 2024 and 2018, respectively. His research interests include processing-in-memory, near-memory computing, and domain-specific computer architectures. He has published more than 60 papers, with over 2,100 citations. He has received HPCA 2025 Best Paper Honorable Mention Award and DATE 2023 Best Paper Nomination.

Abstract: Near-DRAM processing architectures (NDP) addresses the memory wall bottleneck by placing computation close to DRAM, exploiting high internal bandwidth and reducing off-chip data transfers. However, diverse NDP architectures differ in memory hierarchy, processing-unit placement, buffer design, dataflow constraints, and DRAM timing behavior, making efficient deployment difficult. This talk presents our work on simulation, compilation, and deployment optimization for NDP architectures. We first introduce UniNDP, a unified framework for architecture abstraction, instruction generation, cycle-level simulation, and design-space exploration across different NDP systems. We then discuss the challenges and opportunities of bringing NDP into the low-bit floating-point era, and present NDP compiler and data layout optimizations to improve end-to-end performance for low-bit floating-point data-based large language model inference.

Mateusz Juszczak

Poznan University of Technology

"Acceleration of the Prefiltering and Alignment Phases in MMseqs2 Using the Processing-in-Memory Approach"

Short Bio: Mateusz Juszczak is a first-year M.Sc. student in the Faculty of and Telecommunications at Poznan University of Technology, advised by Prof. Paweł T. Wojciechowski. His recent work focuses on hardware-aware programming, computation acceleration, and high-performance computing (HPC). He received his B.Sc. degree in Computer Science in 2026, with a thesis dedicated to implementing data-intensive bioinformatics pipelines on processing-in-memory (PIM) systems.

Abstract: "The rapid digitization of genomics has resulted in the exponential growth of sequence data, creating an urgent need for the efficient processing of Multiple Sequence Alignment (MSA) pipelines. MSA is the process or result of aligning three or more biological sequences, generally proteins, DNA, or RNA. In our project, we focused on MMseqs2 (Many-against-Many sequence searching), a software suite used to search and cluster huge protein and nucleotide sequence sets. We aimed to redesign, implement and evaluate the MMseqs2 suite using novel hardware for massively parallel computation that explores the emerging paradigm of Processing-in-Memory (PIM). The goal of the project was to create a fork of MMseqs2 with added PIM support to accelerate specific processing steps. More precisely, we implemented three DPU-based kernels---k-mer prefiltering, ungapped alignment, and gapped alignment---which are identical in logic to the tools currently available in MMseqs2. We then experimentally evaluated our PIM-accelerated variant of MMseqs2 on the MSA stage of structural biology pipelines, such as those used in ColabFold and AlphaFold. Our results indicate that PIM is a promising approach for end-to-end bioinformatics search pipelines, opening a path to energy-efficient sequence analysis in structural biology and protein prediction."

Call for Presentations

This workshop consists of invited talks on the general topic of memory-centric computing systems. There are a limited number of slots for invited talks. If you would like to deliver a talk on related topics, please contact us by filling out this form.

We invite abstract submissions related to (but not limited to) the following topics in the context of memory-centric computing systems:

• Design of novel and new processing-in-memory (PIM) architectures, including system solutions for real state-of-the-art PIM devices
• Analysis and mapping of novel applications to state-of-the-art PIM systems
• Programming models and code generation support for PIM
• Runtime engines for adaptive code and data scheduling, data mapping, access control for PIM systems
• Memory coherence mechanisms for collaborative host–PIM execution
• Virtual memory support for a unified host and PIM address space
• Data structures and algorithms for PIM systems
• Infrastructures to assess the benefits and feasibility of PIM systems, including benchmarks and simulation infrastructures for PIM prototyping
• Issues related to robustness and security of PIM systems
• Experimental analysis and benchmarking of real PIM systems

Please submit your talk abstract by filling out this form.

Key Dates

Livestream

Organizers

Ismail Emir Yuksel

ETH Zürich

Ismail Emir Yuksel is a 2nd-year PhD student in the SAFARI Research Group at ETH Zurich under the supervision of Prof. Onur Mutlu. His current broader research interests are in computer architecture, processing-in-memory, and hardware security, focusing on understanding, enhancing, and exploiting fundamental computational capabilities of modern DRAM architectures. His recent publications show that commodity DRAM chips, without any modification to the chip itself (only with modifications to the memory controller), are able to execute bulk-bitwise computation and data movement operations (including NAND, NOR, NOT, AND, OR, MAJority, multi-row copy, and initialization functions) in a reasonably robust manner.

📧 ismail.yuksel@safari.ethz.ch

F. Nisa Bostanci

ETH Zürich

F. Nisa Bostanci is a fourth-year PhD student in the SAFARI Research Group at ETH Zurich, under the supervision of Prof. Onur Mutlu. She is broadly interested in computer architecture and, more specifically, in security, reliability, and safety (robustness) of memory systems, emerging memory and computation paradigms, including Processing-In-Memory architectures (PIM), and designing effective and efficient solutions to address robustness issues in modern and future systems. Her recent works uncover and mitigate new security vulnerabilities that emerge with the adoption of read disturbance solutions and PIM architectures to aid in designing robust future systems.

📧 nisa.bostanci@safari.ethz.ch

Ataberk Olgun

ETH Zürich

Ataberk Olgun is a senior PhD student at ETH Zurich, working with Prof. Onur Mutlu. His broad research interests include designing secure, high-performance, and energy-efficient DRAM architectures. Especially with the worsening RowHammer vulnerability, it is increasingly difficult to design new DRAM architectures that satisfy all three characteristics. His current research focuses on i) deeply understanding and ii) efficiently mitigating the RowHammer vulnerability in modern systems.

📧 ataberk.olgun@safari.ethz.ch

Professor Onur Mutlu

ETH Zürich

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He previously held the William D. and Nancy W. Strecker Early Career Professorship at Carnegie Mellon University. His research interests are in computer architecture, computing systems, hardware security, memory & storage systems, and bioinformatics, with a major focus on designing fundamentally energy-efficient, high-performance, and robust computing systems. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held product, research and visiting positions at Intel Corporation, Advanced Micro Devices, VMware, Google, and Stanford University. He received various honors for his research, including the 2025 IEEE Computer Society Harry H. Goode Memorial Award “for seminal contributions to computer architecture research and practice, especially in memory systems.” He is an ACM Fellow, IEEE Fellow, and an elected member of the Academy of Europe. He enjoys teaching, mentoring, and enabling & democratizing access to high-quality research and education. He has supervised 25 PhD graduates, many of whom received major dissertation awards, 18 postdoctoral trainees, and more than 70 Master’s and Bachelor’s students. His computer architecture and digital logic design course lectures and materials are freely available on YouTube and his research group makes a wide variety of artifacts freely available online. For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.

📧 onur.mutlu@safari.ethz.ch

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